Bus protocol reference for OpenCores-era reusable IP.
opencoresAuto indexedpublic-domain-like per OpenCores WISHBONE page
Manual review is required.
/cores
Core comparison
Comparison helps you see quickly which core carries less license, review, and integration risk.
Decision matrix
How to read the matrixStart with review status, license clarity, and warnings. If records are close, then look at tests, board evidence, and toolchain fit.2/4OpenCores UART16550
M1-M3 candidateCanonical UART reference and common FuseSoC adaptations.
opencoresAuto indexedunknown until checked
The license requires manual review.
The source appears stale or legacy.
| Signal | OpenCores Wishbone | OpenCores UART16550 |
|---|---|---|
| Category / source | bus/Wishbone opencores | peripheral/UART opencores |
| Review / maturity | Auto indexed M6 | Auto indexed M1-M3 candidate |
| License | public-domain-like per OpenCores WISHBONE pageManual review required | unknown until checkedManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: YesFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: YesBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownWishbone | UARTunknown |
| Toolchains | unknown | FuseSoC, Verilator |
| Warnings |
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