Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | Orthogone ULL Ethernet MAC/PCS 1G-100G with optional RS-FEC | uart verilog by alexforencich |
|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested |
| License | Commercial license; encrypted RTL (closed source) · Custom license | MIT · Commercial-friendly |
| Language | Verilog | — |
| Tests | — | yes |
| CI | — | yes |
| Formal | — | — |
| FuseSoC | — | — |
| Activity | — | updated 2 years ago |
| Boards | — | — |
| Interfaces | Ethernet 1G/10G/25G/40G/100G, AXI-4 Stream, Serial transceiver (GTY), AXI4-Stream | UART |
| Category | Interfaces and peripherals | Interfaces and peripherals |