Orthogone ULL Ethernet MAC/PCS 1G-100G with optional RS-FEC

Worth knowing

Facts

The source is not on GitHub — an editor checks tests and license manually.

Maturity

M1 · Prototype

License

Commercial license; encrypted RTL (closed source) · Custom license

Tests

not found

CI

not found

Formal verification

not found

FuseSoC

not found

Source exists, but no tests were found. How maturity is assigned

Purpose

Boards

No one has confirmed a board run yet.

Sources

• Orthogone ULL Ethernet MAC/PCS IP cores support 1G, 10G, 25G and 40/100G data rates with optional RS-FEC at 25G and 100G… · 2026-10-02
• Soft PCS logic interfaces with a standard serial transceiver at 1.25, 10.3125 and 25.78125 Gbps; features include FCS in… · 2026-10-02
• 10G MAC/PCS: wire-to-wire round-trip latency 17.1 ns (16b SERDES, 16b AXI-4 Stream; GTY + MAC/PCS, TxSoP to RxSoF, seria… · 2026-10-02
• 40G / 100G (RS-FEC off) / 100G (RS-FEC on) wire-to-wire round-trip latency: 315 ns / 196 ns / 399 ns; 44.2k LUTs, 43.6k… · 2026-10-02
• The vendor states the cores are built from unified Verilog source that scales from 1G to 100G, are IEEE 802.3 compliant,… · 2026-10-02
• 10G MAC/PCS page: AXI-4 Stream 16b at about 644 MHz or 32b at about 322 MHz; high timing margin at 322 MHz and adequate… · 2026-10-02
• The release states the kit ships with encrypted RTL source and is licensed per project, site, corporate, annualized or p… · 2026-10-02