Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | Orthogone ULL PCIe circular-buffer DMA controller (Gen3/Gen4) | LiteSPI | uart verilog by alexforencich |
|---|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested | M2 · Simulation-tested |
| License | Commercial license; encrypted RTL (closed source) · Custom license | BSD-2-Clause · Commercial-friendly | MIT · Commercial-friendly |
| Language | Verilog | Migen/Python/Verilog | — |
| Tests | — | yes | yes |
| CI | — | yes | yes |
| Formal | — | — | — |
| FuseSoC | — | — | — |
| Activity | — | updated 8 days ago | updated 2 years ago |
| Boards | — | — | — |
| Interfaces | PCIe Gen3/Gen4, AXI-4 Stream, AXI4-Stream, PCIe | SPI/QSPI | UART |
| Category | Interfaces and peripherals | Interfaces and peripherals | Interfaces and peripherals |