Orthogone ULL PCIe circular-buffer DMA controller (Gen3/Gen4)

Worth knowing

Facts

The source is not on GitHub — an editor checks tests and license manually.

Maturity

M1 · Prototype

License

Commercial license; encrypted RTL (closed source) · Custom license

Tests

not found

CI

not found

Formal verification

not found

FuseSoC

not found

Source exists, but no tests were found. How maturity is assigned

Purpose

Boards

No one has confirmed a board run yet.

Sources

• The ULL PCIe DMA Controller provides bidirectional data transfer between FPGA and host CPU over PCIe, using cut-through… · 2026-10-02
• Minimum round-trip time 585 ns (Intel Core i9-14900KS host), 608 ns (Intel Xeon w7-2495X) and 635 ns (Intel Xeon Gold 53… · 2026-10-02
• Highly parametrizable: number of channels, queues per channel, queue memory size, AXI-4 Stream bus width, synchronous or… · 2026-10-02
• A Linux kernel module (rpm, deb packages) and a library API for buffer creation, transmission and reception are provided… · 2026-10-02
• The press release describes the circular-buffer DMA controller as moving data between host and FPGA over PCIe Gen3/Gen4. · 2026-10-02
• The release states the kit ships with encrypted RTL source and is licensed per project, site, corporate, annualized or p… · 2026-10-02