Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | Orthogone ULL 10G TCP/IP and UDP/IP Offload Engine | uart verilog by alexforencich |
|---|---|---|
| Maturity | M1 · Prototype | M2 · Simulation-tested |
| License | Commercial license; encrypted RTL (closed source) · Custom license | MIT · Commercial-friendly |
| Language | Verilog | — |
| Tests | — | yes |
| CI | — | yes |
| Formal | — | — |
| FuseSoC | — | — |
| Activity | — | updated 2 years ago |
| Boards | — | — |
| Interfaces | 10G Ethernet MAC (AXI-4 Stream), AXI-4 Stream, AXI4-Stream | UART |
| Category | Interfaces and peripherals | Interfaces and peripherals |