Orthogone ULL 10G TCP/IP and UDP/IP Offload Engine

Worth knowing

Facts

The source is not on GitHub — an editor checks tests and license manually.

Maturity

M1 · Prototype

License

Commercial license; encrypted RTL (closed source) · Custom license

Tests

not found

CI

not found

Formal verification

not found

FuseSoC

not found

Source exists, but no tests were found. How maturity is assigned

Purpose

Boards

No one has confirmed a board run yet.

Sources

• Orthogone offers three FPGA IP core versions under standard licensing: TCP/IP Offload Engine, UDP/IP Offload Engine and… · 2026-10-02
• Full RTL implementation of Layers 2, 3 and 4 (ARP, IPv4, ICMP, TCP, UDP) with session management; configurable number of… · 2026-10-02
• MAC-side interface: 16b AXI-4 at 644 MHz or 32b AXI-4 at 322 MHz; on-chip application interface 32b AXI-4 at 322 MHz (cu… · 2026-10-02
• Tx and Rx processing latency 6.2 ns each in cut-through mode on the AMD x3522pv platform (vendor figure). · 2026-10-02
• The vendor states the cores are verified with a UVM environment and tested for interoperability against network test equ… · 2026-10-02
• The release states the kit ships with encrypted RTL source and is licensed per project, site, corporate, annualized or p… · 2026-10-02