Compare cores

Up to four cores side by side: maturity, license, tests and activity.

AttributePicoRV32VexiiRiscvBlackParrotSERV
MaturityM2 · Simulation-testedM2 · Simulation-testedM2 · Simulation-testedM4 · Production-ready
LicenseISC · Commercial-friendlyMIT · Commercial-friendlyBSD-3-Clause · Commercial-friendlyISC · Commercial-friendly
LanguageVerilogSpinalHDL (Scala)—Verilog
Testsyesyesyesyes
CIyesyesyesyes
Formal——yes—
FuseSoCyes——yes
Activityupdated 25 days agoupdated 4 days agoupdated 1 day agoupdated 38 days ago
Boards————
Interfaces—AXI4, Wishbone, Tilelink, AXI4, Wishbone, Tilelink——
CategoryCPUs and computeCPUs and computeCPUs and computeCPUs and compute