Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | stream_utils | verilog-axis | wb_intercon | colibri |
|---|---|---|---|---|
| Maturity | M2 · Simulation-tested | M2 · Simulation-tested | M2 · Simulation-tested | M1 · Prototype |
| License | ISC · Commercial-friendly | MIT · Commercial-friendly | ISC · Commercial-friendly | CERN-OHL-W-2.0 · Copyleft |
| Language | — | — | — | VHDL-2008 |
| Tests | yes | yes | yes | — |
| CI | — | yes | — | — |
| Formal | — | — | — | — |
| FuseSoC | yes | — | yes | — |
| Activity | updated 12 months ago | updated 2 years ago | updated 7 months ago | — |
| Boards | — | — | — | — |
| Interfaces | FIFO/stream | FIFO/stream, AXI | Wishbone | UART, SPI, I2C, JTAG, Avalon-ST, AXI4-Stream, Wishbone B4, Aurora 64b/66b, Avalon-ST, AXI4-Stream, Wishbone B4 |
| Category | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure |