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Core comparison

Comparison helps you see quickly which core carries less license, review, and integration risk.

Decision matrix

How to read the matrixStart with review status, license clarity, and warnings. If records are close, then look at tests, board evidence, and toolchain fit.2/4

Surelog

M0-M2

SystemVerilog parsing support signal.

githubUnreviewedunknown
Remove from comparison
Warning

The license requires manual review.

High

This is not confirmed to be a reusable RTL core.

OpenCores UART16550

M1-M3 candidate

Canonical UART reference and common FuseSoC adaptations.

opencoresAuto indexedunknown until checked
Remove from comparison
Warning

The license requires manual review.

High

The source appears stale or legacy.

SignalSurelogOpenCores UART16550
Category / sourcetooling/SystemVerilog parser
github		peripheral/UART
opencores
Review / maturityUnreviewed
M0-M2		Auto indexed
M1-M3 candidate
License
unknownUnknown
unknown until checkedManual review required
Evidence / boards
EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees.
EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees.
Board status
unknown
unknown
Tests / CI / formal
Tests: NoCI: NoFormal: No
Tests: NoCI: NoFormal: No
Docs / FuseSoC / board demo
Docs: NoFuseSoC: NoBoard demo: No
Docs: YesFuseSoC: YesBoard demo: No
Signals
QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification
QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification
Interfaces / buses
unknownunknown
UARTunknown
ToolchainsVerilatorFuseSoC, Verilator
Warnings
  • The license requires manual review.
  • This is not confirmed to be a reusable RTL core.
  • The license requires manual review.
  • The source appears stale or legacy.