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Up to four cores side by side: maturity, license, tests and activity.

Attributetaxicolibri
MaturityM2 · Simulation-testedM1 · Prototype
LicenseCERN-OHL-S-2.0 · CopyleftCERN-OHL-W-2.0 · Copyleft
Language—VHDL-2008
Testsyes—
CIyes—
Formal——
FuseSoC——
Activityupdated 35 days ago—
Boards——
InterfacesFIFO/stream, AXIUART, SPI, I2C, JTAG, Avalon-ST, AXI4-Stream, Wishbone B4, Aurora 64b/66b, Avalon-ST, AXI4-Stream, Wishbone B4
CategoryBuses and infrastructureBuses and infrastructure

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