Compare cores
Up to four cores side by side: maturity, license, tests and activity.
| Attribute | wb_intercon | colibri | OpenTitan prim library | verilog-axi |
|---|---|---|---|---|
| Maturity | M2 · Simulation-tested | M1 · Prototype | M4 · Production-ready | M2 · Simulation-tested |
| License | ISC · Commercial-friendly | CERN-OHL-W-2.0 · Copyleft | Apache-2.0 · Commercial-friendly | MIT · Commercial-friendly |
| Language | — | VHDL-2008 | — | — |
| Tests | yes | — | yes | yes |
| CI | — | — | yes | yes |
| Formal | — | — | yes | — |
| FuseSoC | yes | — | yes | — |
| Activity | updated 7 months ago | — | updated 1 day ago | updated 2 years ago |
| Boards | — | — | — | — |
| Interfaces | Wishbone | UART, SPI, I2C, JTAG, Avalon-ST, AXI4-Stream, Wishbone B4, Aurora 64b/66b, Avalon-ST, AXI4-Stream, Wishbone B4 | — | AXI |
| Category | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure | Buses and infrastructure |