OpenTitan UART IP
Checked on GitHubOpenTitan UART documentation.
Interfaces and peripheralsApache-2.0M4 · Production-readyupdated today
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
OpenTitan I2C IP
Checked on GitHubI2C reference with docs.
Interfaces and peripheralsApache-2.0M4 · Production-readyupdated today
OpenTitan SPI device IP
Checked on GitHubSPI device reference.
Interfaces and peripheralsApache-2.0M4 · Production-readyupdated today
uart verilog by alexforencich
Checked on GitHubCommon GitHub UART implementation.
Interfaces and peripheralsMITM2 · Simulation-testedupdated 2 years ago
LiteSPI
Checked on GitHubCommon SPI/SPI flash block in LiteX designs.
Interfaces and peripheralsMigen/Python/VerilogBSD-2-ClauseM2 · Simulation-testedupdated 8 days ago
verilog-ethernet
Checked on GitHubEthernet MAC/UDP/IP stack candidate.
Interfaces and peripheralsMITM2 · Simulation-testedupdated 2 years ago
verilog-i2c
Checked on GitHubI2C core alternative.
Interfaces and peripheralsMITM2 · Simulation-testedupdated 2 years ago
verilog-pcie
Checked on GitHubPCIe endpoint/DMA candidate.
Interfaces and peripheralsMITM2 · Simulation-testedupdated 2 years ago
IObundle Ethernet
Checked on GitHubEthernet candidate with OpenCores ethmac relation.
Interfaces and peripheralsCERN-OHL-S-2.0M4 · Production-readyupdated 11 days ago
Commercial PCIe DMA IP between FPGA and host with kernel-bypass Linux driver; encrypted RTL, commercial license.
Interfaces and peripheralsVerilogCustom licenseM1 · Prototype
Commercial 10G TCP/IP and UDP/IP offload engine IP (L2-L4) with AXI-4 Stream interfaces; encrypted RTL, commercial license.
Interfaces and peripheralsVerilogCustom licenseM1 · Prototype
Commercial Ethernet MAC/PCS IP for 1G to 100G with optional RS-FEC at 25G and 100G; encrypted RTL, commercial license.
Interfaces and peripheralsVerilogCustom licenseM1 · Prototype
IObundle UART16550
Checked on GitHubModern adaptation of OpenCores UART16550.
Interfaces and peripheralsNo license foundM4 · Production-readyupdated 11 days ago
LiteEth
Checked on GitHubModern Ethernet core comparison point.
Interfaces and peripheralsMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 4 days ago
LiteICLink
Checked on GitHubLiteX complex link core.
Interfaces and peripheralsNo license foundM2 · Simulation-testedupdated 4 days ago
LitePCIe
Checked on GitHubOpen PCIe ecosystem core.
Interfaces and peripheralsMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 8 days ago
SPI core alternative.
Interfaces and peripheralsNo license foundM1 · Prototype
PWM category seed.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Small SPI alternative.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Canonical UART reference and common FuseSoC adaptations.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Important comparison point for LiteEth and IObundle Ethernet.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Common small peripheral for beginner/professional comparison.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Common reusable peripheral baseline.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
CAN/LIN category seed.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype