The license requires manual review.
P0M1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.Auto indexedgithub
ZipCPU
CPU, Wishbone and formal-heavy ecosystem.
Primary risk
How to read riskThe risk banner compresses license clarity and review state into a short verdict. Integration decisions still need tests, synthesis, and board evidence.There are blocking license or reuse risksCommercial use is not confirmed.
No clear licenseAuto indexed
Warnings
1Purpose and boundaries
CPU, Wishbone and formal-heavy ecosystem.
Core kind and readiness
Readiness focusIf the status is not yet reproduced, close license, tests, and board-level evidence gaps first. The fields below are for quick scope checking.Core kind
processorVerilog
Interfaces / buses / flow
unknownWishboneVerilator
Still missing before production
5- There is no confirmed HDL/license position for reuse.
- A manual reviewer pass is still needed beyond seed metadata.
- No reproducible tests or CI smoke are confirmed yet.
- Documentation does not yet look sufficient for quick integration.
- There is no board-level evidence with real constraints/report data yet.
Scores
What scores meanEach scale is independent. High usefulness does not cancel a license blocker, and high confidence does not replace board evidence.Quality46
Usefulness72
Integration52
Verification40
Docs40
License25
Beginner42
Professional56
RAG78
Confidence40
Engineering signals
Signals legendSignals show whether useful engineering artefacts are visible. "Yes" does not imply completeness, and "No" often means missing evidence rather than impossible support.TestsCurrent metadata does not show reproducible test evidence yet.
CICurrent metadata does not show confirmed CI yet.
FormalFormal checks or property verification evidence is visible.
DocsDocumentation is not evidence-confirmed yet.
FuseSoCFuseSoC packaging has not been found yet.
Board demoBoard-level demo or target evidence is not confirmed yet.
Open flowOpen-source FPGA flow compatibility is not confirmed yet.
CommercialCommercial use needs manual license review.
License matrix
Why split by scopeHDL, docs, tests, and generated artifacts can carry different terms. Commercial use is split out so each card does not repeat the same prose.HDLHDLUnknown: license evidence is missing for this scope.
DocumentationDocumentationUnknown: license evidence is missing for this scope.
TestsTestsUnknown: license evidence is missing for this scope.
ExamplesExamplesUnknown: license evidence is missing for this scope.
ArtifactsArtifactsUnknown: license evidence is missing for this scope.
Commercial useCommercial useunknown_or_manual_review_required: license value from current metadata.
Board compatibility
Compatibility is still unknownSynthesis/implementation evidence and reproducible board reports are still needed.
Evidence matrix
How to read evidenceEach group only shows confirmed links. The confidence floor is a lower trust bound, not an absolute verdict.Source
confidence 2/5Local verification
1- Try a synthesis smoke run with: Verilator.