Materials
66 found
- RecordingAccess not confirmedMethod for achieving phase determinism in the transmission side of AMD transceivers
Edoardo Orzes
Source: indico.cern.ch - SlidesAccess not confirmedMethod for achieving phase determinism in the transmission side of AMD transceivers
Edoardo Orzes
Source: indico.cern.ch - SlidesAccess not confirmedProspects of RFSoC technology in astroparticle physics experiments
Alexander Novikov (University of Delaware)
Source: indico.cern.ch - RecordingAccess not confirmedProspects of RFSoC technology in astroparticle physics experiments
Alexander Novikov (University of Delaware)
Source: indico.cern.ch - SlidesAccess not confirmedFPGA firmware design and verification for the ATLAS Liquid Argon Calorimeter trigger processor
Lucca Oliveira Facio Viccini (CERN), Marcos Vinicius Silva Oliveira (Brookhaven National Laboratory (US)), Melissa Aguiar (Federal University of Juiz de Fora (BR))
Source: indico.cern.ch - RecordingAccess not confirmedFPGA firmware design and verification for the ATLAS Liquid Argon Calorimeter trigger processor
Lucca Oliveira Facio Viccini (CERN), Marcos Vinicius Silva Oliveira (Brookhaven National Laboratory (US)), Melissa Aguiar (Federal University of Juiz de Fora (BR))
Source: indico.cern.ch - SlidesAccess not confirmedA Neural Network-based trigger for detecting ultra-high-energy neutrinos for RNO-G and IceCube-Gen2
Pawel Marciniewski (Uppsala University), Mr Pawel Marciniewski (Uppsala University)
Source: indico.cern.ch - RecordingAccess not confirmedA Neural Network-based trigger for detecting ultra-high-energy neutrinos for RNO-G and IceCube-Gen2
Pawel Marciniewski (Uppsala University), Mr Pawel Marciniewski (Uppsala University)
Source: indico.cern.ch - SlidesAccess not confirmedArtificial Intelligence workflows for FPGA & SoC using a Deep Learning Processor
Stephan van Beek (MathWorks)
Source: indico.cern.ch - RecordingAccess not confirmedTree Tensor Network inference on FPGA
Lorenzo Borella (Universita e INFN, Padova (IT))
Source: indico.cern.ch - SlidesAccess not confirmedTree Tensor Network inference on FPGA
Lorenzo Borella (Universita e INFN, Padova (IT))
Source: indico.cern.ch - SlidesAccess not confirmedPorting MADGRAPH to FPGA using High-Level Synthesis (HLS)
Hector Gutierrez Arance (Univ. of Valencia and CSIC (ES))
Source: indico.cern.ch - RecordingAccess not confirmedPorting MADGRAPH to FPGA using High-Level Synthesis (HLS)
Hector Gutierrez Arance (Univ. of Valencia and CSIC (ES))
Source: indico.cern.ch - RecordingAccess not confirmedTransferring HLS-generated BDT model into existing firmware in the ATLAS Level-1 trigger
David Reikher (Tel Aviv University (IL))
Source: indico.cern.ch - SlidesAccess not confirmedTransferring HLS-generated BDT model into existing firmware in the ATLAS Level-1 trigger
David Reikher (Tel Aviv University (IL))
Source: indico.cern.ch - RecordingAccess not confirmedHardware acceleration for fast Magnetic Resonance Fingerprinting map reconstruction: FPGA porting of a deep learning algorithm
Mattia Ricchi (University of Pisa & INFN, Bologna (IT)), Camilla Marella (University of Bologna)
Source: indico.cern.ch - SlidesAccess not confirmedHardware acceleration for fast Magnetic Resonance Fingerprinting map reconstruction: FPGA porting of a deep learning algorithm
Mattia Ricchi (University of Pisa & INFN, Bologna (IT)), Camilla Marella (University of Bologna)
Source: indico.cern.ch - SlidesAccess not confirmedResource-efficient FPGA implementation of a channelization stage for superconducting quantum detectors DAQ systems
Timo Muscheid
Source: indico.cern.ch - RecordingAccess not confirmedResource-efficient FPGA implementation of a channelization stage for superconducting quantum detectors DAQ systems
Timo Muscheid
Source: indico.cern.ch - SlidesAccess not confirmedQibosoq: an open-source framework for quantum circuit RFSoC programming
Rodolfo Carobene
Source: indico.cern.ch
Materials checked:
Hosted at CERN, the forum focuses on how FPGA designs are built and verified. The completed timetable provides recordings and presentation files from the technical sessions.