Materials
66 found
- RecordingAccess not confirmedQibosoq: an open-source framework for quantum circuit RFSoC programming
Rodolfo Carobene
Source: indico.cern.ch - SlidesAccess not confirmedHigh-Level Synthesis for Machine Learning
Nicolo Ghielmetti (CERN)
Source: indico.cern.ch - RecordingAccess not confirmedHigh-Level Synthesis for Machine Learning
Nicolo Ghielmetti (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedUnder the Canopy: Exploring Conifer for Low-Latency Decision Forests on FPGAs
Sioni Paris Summers (CERN)
Source: indico.cern.ch - RecordingAccess not confirmedUnder the Canopy: Exploring Conifer for Low-Latency Decision Forests on FPGAs
Sioni Paris Summers (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedUVVM – An introduction to the world’s fastest growing FPGA verification methodology
Espen Tallaksen
Source: indico.cern.ch - RecordingAccess not confirmedUVVM – An introduction to the world’s fastest growing FPGA verification methodology
Espen Tallaksen
Source: indico.cern.ch - SlidesAccess not confirmedLoCod: an open-source hardware/software co-design tool for SoC/FPGA
Florent Manni (CNES)
Source: indico.cern.ch - RecordingAccess not confirmedLoCod: an open-source hardware/software co-design tool for SoC/FPGA
Florent Manni (CNES)
Source: indico.cern.ch - RecordingAccess not confirmedYML2HDL tool
Thiago Costa De Paiva (University of Massachusetts (US))
Source: indico.cern.ch - SlidesAccess not confirmedYML2HDL tool
Thiago Costa De Paiva (University of Massachusetts (US))
Source: indico.cern.ch - SlidesAccess not confirmedAutomatic code generation for managing the firmware and software for configuration/status registers and memories in the ATLAS Level-1 Central Trigger
Anna Malgorzata Kulinska (CERN)
Source: indico.cern.ch - RecordingAccess not confirmedAutomatic code generation for managing the firmware and software for configuration/status registers and memories in the ATLAS Level-1 Central Trigger
Anna Malgorzata Kulinska (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedAssertion-Based Formal Debugging During RTL Development
N. Engelhardt (YosysHQ)
Source: indico.cern.ch - RecordingAccess not confirmedAssertion-Based Formal Debugging During RTL Development
N. Engelhardt (YosysHQ)
Source: indico.cern.ch - RecordingAccess not confirmedOpen source formal verification with SymbiYosis
Yann Thoma (HEIG-VD)
Source: indico.cern.ch - SlidesAccess not confirmedOpen source formal verification with SymbiYosis
Yann Thoma (HEIG-VD)
Source: indico.cern.ch - SlidesAccess not confirmedBecoming vendor agnostic with the help of model-based source code generation
Alexander Wirthmüller (MPSI Technologies GmbH)
Source: indico.cern.ch - RecordingAccess not confirmedBecoming vendor agnostic with the help of model-based source code generation
Alexander Wirthmüller (MPSI Technologies GmbH)
Source: indico.cern.ch - SlidesAccess not confirmedHDL on git (Hog)
Nordin Aranzabal Barrio
Source: indico.cern.ch
Materials checked:
Hosted at CERN, the forum focuses on how FPGA designs are built and verified. The completed timetable provides recordings and presentation files from the technical sessions.