Materials
77 found
- SlidesAccess not confirmedWelcome to the 2nd FPGA Developers' Forum
Davide Cieri (Max Planck Society (DE))
Source: indico.cern.ch - RecordingAccess not confirmedWelcome to the 2nd FPGA Developers' Forum
Davide Cieri (Max Planck Society (DE))
Source: indico.cern.ch - SlidesAccess not confirmedWelcome to CERN
Evangelia Gousiou (CERN)
Source: indico.cern.ch - RecordingAccess not confirmedWelcome to CERN
Evangelia Gousiou (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedThe future of FPGAs in HEP detectors for FCC and beyond
Sophie Baron (CERN)
Source: indico.cern.ch - RecordingAccess not confirmedThe future of FPGAs in HEP detectors for FCC and beyond
Sophie Baron (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedOpen Logic – open-source FPGA Standard Library
Oliver Bründler (OpenLogic)
Source: indico.cern.ch - RecordingAccess not confirmedOpen Logic – open-source FPGA Standard Library
Oliver Bründler (OpenLogic)
Source: indico.cern.ch - RecordingAccess not confirmedUnleashing >100G Performance: High-Speed UDP/TCP Hardware Stacks for FPGAs by CAST
Calliope-Louisa Sotiropoulou (CAST)
Source: indico.cern.ch - SlidesAccess not confirmedUnleashing >100G Performance: High-Speed UDP/TCP Hardware Stacks for FPGAs by CAST
Calliope-Louisa Sotiropoulou (CAST)
Source: indico.cern.ch - SlidesAccess not confirmedThe PandABlocks framework for flexible run-time configuration of Zynq SoCs
Glenn Christian (Diamond Light Source)
Source: indico.cern.ch - RecordingAccess not confirmedThe PandABlocks framework for flexible run-time configuration of Zynq SoCs
Glenn Christian (Diamond Light Source)
Source: indico.cern.ch - SlidesAccess not confirmedNDK: An open-source framework for high-speed network applications on FPGAs
Daniel Kondys (CESNET), Radek Iša (CESNET)
Source: indico.cern.ch - RecordingAccess not confirmedNDK: An open-source framework for high-speed network applications on FPGAs
Daniel Kondys (CESNET), Radek Iša (CESNET)
Source: indico.cern.ch - SlidesAccess not confirmedError-Redundant Implementation of Commercial IP Cores: A Practical Example
Mr Philipp Jacobsohn (SmartDV)
Source: indico.cern.ch - RecordingAccess not confirmedError-Redundant Implementation of Commercial IP Cores: A Practical Example
Mr Philipp Jacobsohn (SmartDV)
Source: indico.cern.ch - SlidesAccess not confirmedExploring Linearity and Temperature Stability in Time-to-Digital Converters
Gian-Luca Brazerol (Ostschweizer Fachhochschule)
Source: indico.cern.ch - RecordingAccess not confirmedExploring Linearity and Temperature Stability in Time-to-Digital Converters
Gian-Luca Brazerol (Ostschweizer Fachhochschule)
Source: indico.cern.ch - SlidesAccess not confirmedImplementation of Time to Digital Converter on FPGA for high-resolution-performance in Particle Therapy applications
Mr ARASH AMINI BARDPAREH (Politecnico di Torino)
Source: indico.cern.ch - RecordingAccess not confirmedImplementation of Time to Digital Converter on FPGA for high-resolution-performance in Particle Therapy applications
Mr ARASH AMINI BARDPAREH (Politecnico di Torino)
Source: indico.cern.ch
Materials checked:
Hosted at CERN, the forum focuses on how FPGA designs are built and verified. The completed timetable provides recordings and presentation files from the technical sessions.