Materials
77 found
- SlidesAccess not confirmedA low latency Gated Recurrent Unit Implementation for the AMD Versal AI Engine
Michail Sapkas (Universita e INFN, Padova (IT))
Source: indico.cern.ch - RecordingAccess not confirmedA low latency Gated Recurrent Unit Implementation for the AMD Versal AI Engine
Michail Sapkas (Universita e INFN, Padova (IT))
Source: indico.cern.ch - RecordingAccess not confirmedWhere Innovation Meets Reliability – FPGA based solutions by Trenz Electronic
Thomas Brünger (Trenz Electronic GmbH)
Source: indico.cern.ch - SlidesAccess not confirmedWhere Innovation Meets Reliability – FPGA based solutions by Trenz Electronic
Thomas Brünger (Trenz Electronic GmbH)
Source: indico.cern.ch - SlidesAccess not confirmedDistributed Arithmetic for Real-time Neural Networks on FPGAs
Chang Sun (California Institute of Technology (US))
Source: indico.cern.ch - RecordingAccess not confirmedDistributed Arithmetic for Real-time Neural Networks on FPGAs
Chang Sun (California Institute of Technology (US))
Source: indico.cern.ch - Source codeAccess not confirmedChisel4ml: Generating Fast Implementations of Deeply Quantized Neural Networks using Chisel Generators
Jure Vreča (Jožef Stefan Institute)
Source: indico.cern.ch - SlidesAccess not confirmedChisel4ml: Generating Fast Implementations of Deeply Quantized Neural Networks using Chisel Generators
Jure Vreča (Jožef Stefan Institute)
Source: indico.cern.ch - RecordingAccess not confirmedChisel4ml: Generating Fast Implementations of Deeply Quantized Neural Networks using Chisel Generators
Jure Vreča (Jožef Stefan Institute)
Source: indico.cern.ch - SlidesAccess not confirmedA Reconfigurable FPGA-Based ML Library for Kernel Methods
Yousef Alnaser (TU Chemnitz, Fraunhofer ENAS)
Source: indico.cern.ch - RecordingAccess not confirmedA Reconfigurable FPGA-Based ML Library for Kernel Methods
Yousef Alnaser (TU Chemnitz, Fraunhofer ENAS)
Source: indico.cern.ch - SlidesAccess not confirmedAccelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments
Filip Wojcicki (Imperial College London)
Source: indico.cern.ch - RecordingAccess not confirmedAccelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments
Filip Wojcicki (Imperial College London)
Source: indico.cern.ch - SlidesAccess not confirmedFPGA Implementation of Next-Generation Reservoir Computing for predicting dynamical systems
João Folhadela (Deutsches Zentrum für Luft- und Raumfahrt e.V. (DLR))
Source: indico.cern.ch - RecordingAccess not confirmedFPGA Implementation of Next-Generation Reservoir Computing for predicting dynamical systems
João Folhadela (Deutsches Zentrum für Luft- und Raumfahrt e.V. (DLR))
Source: indico.cern.ch - Source codeAccess not confirmedFPGA Implementation of Next-Generation Reservoir Computing for predicting dynamical systems
João Folhadela (Deutsches Zentrum für Luft- und Raumfahrt e.V. (DLR))
Source: indico.cern.ch - SlidesAccess not confirmedAbstract interface modelling for better genericity and code clarity
Nicolas Pouillon (Ellisys)
Source: indico.cern.ch - RecordingAccess not confirmedAbstract interface modelling for better genericity and code clarity
Nicolas Pouillon (Ellisys)
Source: indico.cern.ch - SlidesAccess not confirmedDisruptive Efinix Quantum Architecture
Harald Werner (Efinix Inc.)
Source: indico.cern.ch - RecordingAccess not confirmedDisruptive Efinix Quantum Architecture
Harald Werner (Efinix Inc.)
Source: indico.cern.ch
Materials checked:
Hosted at CERN, the forum focuses on how FPGA designs are built and verified. The completed timetable provides recordings and presentation files from the technical sessions.