Materials
77 found
- SlidesAccess not confirmedArchitecting FPGA for low power Leadership
Dr Hardik Shah (Lattice Semiconductor)
Source: indico.cern.ch - RecordingAccess not confirmedArchitecting FPGA for low power Leadership
Dr Hardik Shah (Lattice Semiconductor)
Source: indico.cern.ch - SlidesAccess not confirmedGet the right FPGA quality through efficient Requirements Coverage (aka Specification Coverage)
Espen Tallaksen (EmLogic)
Source: indico.cern.ch - RecordingAccess not confirmedGet the right FPGA quality through efficient Requirements Coverage (aka Specification Coverage)
Espen Tallaksen (EmLogic)
Source: indico.cern.ch - SlidesAccess not confirmedPython-based, flexible testbench for a spacecraft payload
Roberto Rigamonti (HES-SO/HEIG-VD)
Source: indico.cern.ch - RecordingAccess not confirmedPython-based, flexible testbench for a spacecraft payload
Roberto Rigamonti (HES-SO/HEIG-VD)
Source: indico.cern.ch - SlidesAccess not confirmedPractical Methods for Functional Verification
Simone Ponzio (ARM)
Source: indico.cern.ch - RecordingAccess not confirmedPractical Methods for Functional Verification
Simone Ponzio (ARM)
Source: indico.cern.ch - SlidesAccess not confirmedHigh Performance FPGA Solutions – PRO DESIGN, best Choice for Development and Manufacturing
Mr Bernhard Gleissner (proDesign)
Source: indico.cern.ch - RecordingAccess not confirmedHigh Performance FPGA Solutions – PRO DESIGN, best Choice for Development and Manufacturing
Mr Bernhard Gleissner (proDesign)
Source: indico.cern.ch - RecordingAccess not confirmedWhy Your Team Should be using VHDL + OSVVM for Verification
Jim Lewis (SynthWorks)
Source: indico.cern.ch - SlidesAccess not confirmedWhy Your Team Should be using VHDL + OSVVM for Verification
Jim Lewis (SynthWorks)
Source: indico.cern.ch - RecordingAccess not confirmedSummary of FDF2025 and Awards
Dr Rui Zou (Cornell University (US))
Source: indico.cern.ch - SlidesAccess not confirmedSummary of FDF2025 and Awards
Dr Rui Zou (Cornell University (US))
Source: indico.cern.ch - SlidesAccess not confirmedClosing Remarks
Dr Francesco Gonnella (University of Birmingham (GB))
Source: indico.cern.ch - RecordingAccess not confirmedClosing Remarks
Dr Francesco Gonnella (University of Birmingham (GB))
Source: indico.cern.ch - DocumentFDF 2025: full timetableSource: indico.cern.ch
Materials checked:
Hosted at CERN, the forum focuses on how FPGA designs are built and verified. The completed timetable provides recordings and presentation files from the technical sessions.