Materials
77 found
- SlidesAccess not confirmedLow Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers
Paul Bachek (Brookhaven National Lab)
Source: indico.cern.ch - RecordingAccess not confirmedLow Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers
Paul Bachek (Brookhaven National Lab)
Source: indico.cern.ch - SlidesAccess not confirmedCERN ABT's lazy git workflow for equipment-specific designs
Léa Strobino (CERN), Pieter Van Trappen (CERN)
Source: indico.cern.ch - RecordingAccess not confirmedStandardizing SoC Development in CERN's accelerator complex: A Build System for Xilinx Platforms
André Pinho (CERN), Irene Degl'Innocenti (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedStandardizing SoC Development in CERN's accelerator complex: A Build System for Xilinx Platforms
André Pinho (CERN), Irene Degl'Innocenti (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedThe new CI4FPGA service at CERN
Christos Gentsos (CERN (IT-CA-GES))
Source: indico.cern.ch - SlidesAccess not confirmedApplication-Specific Arithmetic Operators with the FloPoCo HDL core generator
Florent de Dinechin (INSA-Lyon)
Source: indico.cern.ch - RecordingAccess not confirmedApplication-Specific Arithmetic Operators with the FloPoCo HDL core generator
Florent de Dinechin (INSA-Lyon)
Source: indico.cern.ch - SlidesAccess not confirmedCustomized eFPGAs with FABulous
Dirk Koch (Ruprecht-Karls-Universität Heidelberg)
Source: indico.cern.ch - RecordingAccess not confirmedCustomized eFPGAs with FABulous
Dirk Koch (Ruprecht-Karls-Universität Heidelberg)
Source: indico.cern.ch - SlidesAccess not confirmedAllo: A Python-Embedded Programming Model for Composable Accelerator Design
Hongzheng Chen (Cornell University)
Source: indico.cern.ch - Source codeAccess not confirmedAllo: A Python-Embedded Programming Model for Composable Accelerator Design
Hongzheng Chen (Cornell University)
Source: indico.cern.ch - RecordingAccess not confirmedAllo: A Python-Embedded Programming Model for Composable Accelerator Design
Hongzheng Chen (Cornell University)
Source: indico.cern.ch - SlidesAccess not confirmedGenerating memory maps with Cheby and Reksio
Mr Bartosz Bielawski (CERN), Tristan Gingold (CERN)
Source: indico.cern.ch - RecordingAccess not confirmedGenerating memory maps with Cheby and Reksio
Mr Bartosz Bielawski (CERN), Tristan Gingold (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedHDLRegression: A reliable and efficient tool for FPGA regression testing
Marius Elvegård (Inventas)
Source: indico.cern.ch - RecordingAccess not confirmedHDLRegression: A reliable and efficient tool for FPGA regression testing
Marius Elvegård (Inventas)
Source: indico.cern.ch - SlidesAccess not confirmedCommon Exchange Format for HDL Build Systems
Lieven Lemiengre (Sigasi)
Source: indico.cern.ch - RecordingAccess not confirmedYosysHQ - Building alternative FPGA toolchains
N. Engelhardt (YosysHQ)
Source: indico.cern.ch - SlidesAccess not confirmedYosysHQ - Building alternative FPGA toolchains
N. Engelhardt (YosysHQ)
Source: indico.cern.ch
Materials checked:
Hosted at CERN, the forum focuses on how FPGA designs are built and verified. The completed timetable provides recordings and presentation files from the technical sessions.