Materials
88 found
- SlidesAccess not confirmedWelcome to FDF26
Davide Cieri (Max Planck Society (DE))
Source: indico.cern.ch - RecordingAccess not confirmedWelcome to FDF26
Davide Cieri (Max Planck Society (DE))
Source: indico.cern.ch - RecordingAccess not confirmedWhat Star Trek can teach us about using AI in FPGA design
Mr Adam Taylor (Adiuvo Engineering)
Source: indico.cern.ch - SlidesAccess not confirmedWhat Star Trek can teach us about using AI in FPGA design
Mr Adam Taylor (Adiuvo Engineering)
Source: indico.cern.ch - SlidesAccess not confirmedSponsor Presentations: Sponsor PresentatonSource: indico.cern.ch
- SlidesAccess not confirmedScalable and lightweight RoCEv2 TX FPGA IP core
Gabriele Bortolato (Universita e INFN, Padova (IT))
Source: indico.cern.ch - RecordingAccess not confirmedScalable and lightweight RoCEv2 TX FPGA IP core
Gabriele Bortolato (Universita e INFN, Padova (IT))
Source: indico.cern.ch - RecordingAccess not confirmedThe PoC-Library - Free and Open-Source VHDL IP Core Library
Patrick Lehmann (PLC2)
Source: indico.cern.ch - SlidesAccess not confirmedThe PoC-Library - Free and Open-Source VHDL IP Core Library
Patrick Lehmann (PLC2)
Source: indico.cern.ch - SlidesAccess not confirmedNDK framework: Deep-Diving into High-Throughput Network Monitoring Pipelines
Daniel Kondys (CESNET)
Source: indico.cern.ch - RecordingAccess not confirmedNDK framework: Deep-Diving into High-Throughput Network Monitoring Pipelines
Daniel Kondys (CESNET)
Source: indico.cern.ch - RecordingAccess not confirmedUSB implementation with GateMate FPGA
Anton Kuzmin (gmm7550)
Source: indico.cern.ch - SlidesAccess not confirmedUSB implementation with GateMate FPGA
Anton Kuzmin (gmm7550)
Source: indico.cern.ch - SlidesAccess not confirmedRoCE-Stream -- offloading (debug) data over 100Gbit RoCE RDMA
Alexander Daum (p2l2)
Source: indico.cern.ch - SlidesAccess not confirmedCI-Driven FPGA ML Experimentation: Unified Results from HLS, Implementation, and On-Hardware Testing
Georgios Flengas (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedXiBIF: A Python tool and hardware platform for streamlined FPGA development
Mr Janik Witzig (Ostschweizer Fachhochschule), Lukas Leuenberger (Ostschweizer Fachhochschule)
Source: indico.cern.ch - SlidesAccess not confirmedBenchmarking Neural Network Inference on Versal ACAP AI Engines for Real-Time Detector Alignment
Haider Abidi (Brookhaven National Laboratory (US))
Source: indico.cern.ch - SlidesAccess not confirmedLeveraging HBM for accelerating arbitrary Quantum Simulation on AMD Alveo platforms
Marwin Kirchhofs
Source: indico.cern.ch - SlidesAccess not confirmedTowards a predictable toolchain dedicated to the generation of FPGA circuits for control algorithms
Inès Winandy (ENAC)
Source: indico.cern.ch - SlidesAccess not confirmedQualifying FPGAs for Radiation-Tolerant Applications
Patrick Urban (Cologne Chip AG)
Source: indico.cern.ch
Materials checked:
Hosted at CERN, the forum focuses on how FPGA designs are built and verified. The completed timetable provides recordings and presentation files from the technical sessions.