Materials
88 found
- SlidesAccess not confirmedAn Hardware Emulator for the ATLAS Phase-II L0MDT Trigger System
Marcel Marques Boonen (Max Planck Society (DE))
Source: indico.cern.ch - SlidesAccess not confirmedDeep Memory for the Data Acquisition of the IceCube-Gen2 Surface Array
Frederik Schmitt (Karlsruhe Institut of Technology)
Source: indico.cern.ch - SlidesAccess not confirmedPOEMMA Balloon with Radio experiment as a use case for RFSoC in Astroparticle Physics
Alexander Novikov (University of Delaware)
Source: indico.cern.ch - SlidesAccess not confirmedTransitioning to Modern FPGA Architectures in a High-Throughput Research Facility
Mr Bruno Fernandes (Eur.XFEL (European XFEL))
Source: indico.cern.ch - SlidesAccess not confirmedGeant4-driven realistic waveform generation for FPGA algorithm verification in radiation detector readout
Ms Handan YILMAZ (istanbul technical University)
Source: indico.cern.ch - SlidesAccess not confirmedJEDI-linear: Fast and Efficient Graph Neural Networks for Jet Tagging on FPGAs
Zhiqiang Que (University of Bristol)
Source: indico.cern.ch - SlidesAccess not confirmedReconciling Fixed-Frequency Clocking and Variable Sampling-Rate Data: Real-Time Arbitrary Resampling for Stream Processing
Javier Galindo Guarch (Aragon Institute of Technology Itainnova (ES))
Source: indico.cern.ch - SlidesAccess not confirmedLow-Complexity Median Algorithm in FPGA for AMS-02 Layer-0 Upgrade
Luca Russo (Universita e INFN, Perugia (IT))
Source: indico.cern.ch - SlidesAccess not confirmedAI Inference in FPGAs for both Standard and Safe & Dependable Applications
David Ganz (ZHAW)
Source: indico.cern.ch - SlidesAccess not confirmedSVN is better than GIT for FPGA development: I will die on this hill
Yair Linn (TRIUMF)
Source: indico.cern.ch - SlidesAccess not confirmedMONO: Enhancing Bit-Flip Resilience With Bit Homogeneity for Neural Networks
Maryam Eslami (Ruhr-Universität Bochum)
Source: indico.cern.ch - SlidesAccess not confirmedPandA-Bambu Backend for hls4ml
Nicolo Ghielmetti (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedFrom C/C++ to Hardware with Bambu: An Open-Source HLS Research Tool
Mr Tommaso Fellegara (Politecnico di Milano)
Source: indico.cern.ch - SlidesAccess not confirmedARTEMIS: FPGA-based AD in the ATLAS Level-1 Trigger
Paula Martinez Suarez (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedImplementation of Elias deterministic extractor for true random number generation
Lorenzo Borella (Universita e INFN, Padova (IT))
Source: indico.cern.ch - SlidesAccess not confirmedThe Firmware Development Kit (FDK)
Adam Lee Barcock (Science and Technology Facilities Council STFC (GB))
Source: indico.cern.ch - SlidesAccess not confirmedFrame Buffering Design Strategies for Boosting Mobipix 15D X-Ray Imaging Rates
Mr Allan Borgato (LNLS)
Source: indico.cern.ch - SlidesAccess not confirmedInside UVVM: Architecture and Design of Custom Verification Components
Markus Leiter (p2l2)
Source: indico.cern.ch - RecordingAccess not confirmedInside UVVM: Architecture and Design of Custom Verification Components
Markus Leiter (p2l2)
Source: indico.cern.ch - SlidesAccess not confirmedOpen-source simulation landscape and advances towards mixed language support
Augusto Fraga Giachero (CNPEM / LNLS)
Source: indico.cern.ch
Materials checked:
Hosted at CERN, the forum focuses on how FPGA designs are built and verified. The completed timetable provides recordings and presentation files from the technical sessions.