Materials
88 found
- SlidesAccess not confirmedVHDL-LS - A Free and Open Source Language Server for VHDL
Lukas Scheller (KIT)
Source: indico.cern.ch - RecordingAccess not confirmedVHDL-LS - A Free and Open Source Language Server for VHDL
Lukas Scheller (KIT)
Source: indico.cern.ch - SlidesAccess not confirmedfwk: An Open-Source Framework for Standardized FPGA Development at DESY
Cagil Gumus (DESY)
Source: indico.cern.ch - RecordingAccess not confirmedfwk: An Open-Source Framework for Standardized FPGA Development at DESY
Cagil Gumus (DESY)
Source: indico.cern.ch - SlidesAccess not confirmedDevOps for FPGA 101: from version control to hardware-in-the-loop testing
Matteo Vit (Starware Design)
Source: indico.cern.ch - RecordingAccess not confirmedDevOps for FPGA 101: from version control to hardware-in-the-loop testing
Matteo Vit (Starware Design)
Source: indico.cern.ch - SlidesAccess not confirmedThe CERN Open Hardware Licence for FPGA Designs
Javier Serrano (CERN)
Source: indico.cern.ch - RecordingAccess not confirmedThe CERN Open Hardware Licence for FPGA Designs
Javier Serrano (CERN)
Source: indico.cern.ch - RecordingAccess not confirmedKyokko2: a portable multi-gigabit serial communication controller
Sou Tanaka (Osana Lab)
Source: indico.cern.ch - SlidesAccess not confirmedKyokko2: a portable multi-gigabit serial communication controller
Sou Tanaka (Osana Lab)
Source: indico.cern.ch - SlidesAccess not confirmedA Multigigabit Link Layer Protocol for Single Picosecond Latency Determinism Using AMD Ultrascale+ GTH and GTY Transceivers
Paul Bachek (Brookhaven National Lab)
Source: indico.cern.ch - RecordingAccess not confirmedA Multigigabit Link Layer Protocol for Single Picosecond Latency Determinism Using AMD Ultrascale+ GTH and GTY Transceivers
Paul Bachek (Brookhaven National Lab)
Source: indico.cern.ch - RecordingAccess not confirmedLatency analysis of the CPU-FPGA interface in the Zynq UltraScale+ SoC
Valerio Nappi (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedLatency analysis of the CPU-FPGA interface in the Zynq UltraScale+ SoC
Valerio Nappi (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedRecovered Clock Phase Monitoring on AMD Transceivers for Deterministic Timing
Nikitas Loukas (University of Notre Dame (US))
Source: indico.cern.ch - RecordingAccess not confirmedRecovered Clock Phase Monitoring on AMD Transceivers for Deterministic Timing
Nikitas Loukas (University of Notre Dame (US))
Source: indico.cern.ch - RecordingAccess not confirmedSystemVerilog Hacks: Circumventing the Limitations of SystemVerilog
Yair Linn (TRIUMF)
Source: indico.cern.ch - SlidesAccess not confirmedSystemVerilog Hacks: Circumventing the Limitations of SystemVerilog
Yair Linn (TRIUMF)
Source: indico.cern.ch - SlidesAccess not confirmedCDCs, FIFOs, and Width Converters: How to Combine Open Logic Building Blocks Correctly
Oliver Bründler (Enclustra GmbH)
Source: indico.cern.ch - RecordingAccess not confirmedCDCs, FIFOs, and Width Converters: How to Combine Open Logic Building Blocks Correctly
Oliver Bründler (Enclustra GmbH)
Source: indico.cern.ch
Materials checked:
Hosted at CERN, the forum focuses on how FPGA designs are built and verified. The completed timetable provides recordings and presentation files from the technical sessions.