Materials
88 found
- RecordingAccess not confirmedOpen-source simulation landscape and advances towards mixed language support
Augusto Fraga Giachero (CNPEM / LNLS)
Source: indico.cern.ch - SlidesAccess not confirmedOpen Source HDL Co-Simulation with AMD Alveo
Matthias Kern (p2l2)
Source: indico.cern.ch - RecordingAccess not confirmedOpen Source HDL Co-Simulation with AMD Alveo
Matthias Kern (p2l2)
Source: indico.cern.ch - SlidesAccess not confirmedAMD Embedded AI Solutions
Mr Thomas Gmeinder (AMD)
Source: indico.cern.ch - RecordingAccess not confirmedAMD Embedded AI Solutions
Mr Thomas Gmeinder (AMD)
Source: indico.cern.ch - RecordingAccess not confirmedKalEdge-Lite: Hardware-Aware ML-to-FPGA Deployment with Automated hls4ml Integration
Romina Soledad Molina (kaleidoforge)
Source: indico.cern.ch - SlidesAccess not confirmedHGQ: High Granularity Quantization for Real-time Neural Networks and LUT-Based Inference
Chang Sun (California Institute of Technology (US))
Source: indico.cern.ch - RecordingAccess not confirmedHGQ: High Granularity Quantization for Real-time Neural Networks and LUT-Based Inference
Chang Sun (California Institute of Technology (US))
Source: indico.cern.ch - SlidesAccess not confirmedNGRC on SoC for online learning of dynamical systems
João Folhadela (German Aerospace Center)
Source: indico.cern.ch - RecordingAccess not confirmedNGRC on SoC for online learning of dynamical systems
João Folhadela (German Aerospace Center)
Source: indico.cern.ch - SlidesAccess not confirmedAccelerating Data: Lossless Compression for HPC, Datacenter, AI, and Scientific Data Pipelines
Calliope-Louisa Sotiropoulou (CAST)
Source: indico.cern.ch - RecordingAccess not confirmedAccelerating Data: Lossless Compression for HPC, Datacenter, AI, and Scientific Data Pipelines
Calliope-Louisa Sotiropoulou (CAST)
Source: indico.cern.ch - SlidesAccess not confirmedHigh-speed digital twins: Pushing simulation time-steps into the nanosecond range using Versal ACAP
Pablo Trujillo (controlpaths)
Source: indico.cern.ch - RecordingAccess not confirmedHigh-speed digital twins: Pushing simulation time-steps into the nanosecond range using Versal ACAP
Pablo Trujillo (controlpaths)
Source: indico.cern.ch - SlidesAccess not confirmedStudy of non linearities on the AMD Phase Interpolator
Edoardo Orzes (CERN)
Source: indico.cern.ch - RecordingAccess not confirmedStudy of non linearities on the AMD Phase Interpolator
Edoardo Orzes (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedDynamic Derandomizing Buffer: A Portable and Scalable Solution for Time-Ordered Packet Aggregation
Mitja Vodnik (CERN)
Source: indico.cern.ch - RecordingAccess not confirmedDynamic Derandomizing Buffer: A Portable and Scalable Solution for Time-Ordered Packet Aggregation
Mitja Vodnik (CERN)
Source: indico.cern.ch - SlidesAccess not confirmedTools and libraries Review
Francesco Gonnella (University of Birmingham (GB))
Source: indico.cern.ch - RecordingAccess not confirmedTools and libraries Review
Francesco Gonnella (University of Birmingham (GB))
Source: indico.cern.ch
Materials checked:
Hosted at CERN, the forum focuses on how FPGA designs are built and verified. The completed timetable provides recordings and presentation files from the technical sessions.