Results
Best Project Award (shared): FazyRV-ExoTiny CCX. Team: Meinhard Kissich, Matthias Musch, Sabih Muhammad, Spandan Das, Marcin Kowalczyk.
Source: heichips.github.ioBest Project Award (shared): Waveform + Tone Generation using CORDIC Algorithm. Team: Shankaranarayanan H, Naveen Dhage Shankar, Guha H, Ketan Sanjay Chaudhari.
Source: heichips.github.io
Materials
64 found
- RecordingAccess not confirmedHeiChips 2025 YouTube Playlist
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Source: heichips.github.io - Source codeAccess not confirmedOSS CAD Suite: installation instructions
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Source: heichips.github.io - Source codeAccess not confirmedFABulous FPGA framework: workshop source tree
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Source: heichips.github.io - Source codeAccess not confirmedLibreLane: open-source ASIC implementation flow
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Source: heichips.github.io - Source codeAccess not confirmedFABulator: simulator installation
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Source: heichips.github.io - Source codeAccess not confirmedIIC-OSIC-TOOLS: workshop environment installation
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Source: heichips.github.io - DocumentAccess not confirmedEver wanted to design your own ASIC in VHDL?
Pascal Gesell · en
Source: heichips.github.io - DocumentAccess not confirmedMoodle & Verilator make open-source, web-based automated marking of SystemVerilog labs a reality
Graeme M. Bragg, Jules Field · en
Source: heichips.github.io - DocumentAccess not confirmedProcessing event data from a neuromorphic vision sensor
Marcin Kowalczyk · en
Source: heichips.github.io - DocumentAccess not confirmedLow Cost Power Cycling Stimuli Generator for AMS Validation using an FPGA
Varun Posimsetty · en
Source: heichips.github.io - DocumentAccess not confirmedEMBOSOM Emigrating Embedded Software Security into Modern Emerging Hardware Paradigms
Spandan Das, Christoph Lueth, Tim Gueneysu, Pascal Sasdrich, Rolf Drechsler · en
Source: heichips.github.io - DocumentAccess not confirmedRadar Frequency-Comparison Monopulse Validation Using FPGA-Generated Wideband Chirp Waveforms
Andrea Quirini, Aisha Baloch, Fabia Arshad, Fabiola Colone, Pierfrancesco Lombardo · en
Source: heichips.github.io - DocumentAccess not confirmedMemSim+: Realistic Behavioral Model for ReRAMs Capturing Non-Idealities
Gulafshan · en
Source: heichips.github.io - DocumentAccess not confirmedHardware/Software Co-Analysis for Worst Case Execution Time Bounds
Can Joshua Lehmann, Lars Bauer, Hassan Nassar, Heba Khdr, Jörg Henkel · en
Source: heichips.github.io - DocumentAccess not confirmedA Highly Linear Wide Bandwidth Programmable Gain Amplifier in 0.18μm CMOS Process
Emmanuel Innocent and Dr. O. O. Ilori · en
Source: heichips.github.io - DocumentAccess not confirmedOptimizing Hardware for Neural Network Inference using Virtual Prototypes
Jan Zielasko, Rolf Drechsler · en
Source: heichips.github.io - DocumentAccess not confirmedTOWARDS SCALABLE READOUT IC‘S FOR SEMICONDUCTOR QUANTUM DOTS
Jonas Bühler, Arun Ashok, Lammert Duipmans, Christian Grewing, Dennis Nielinger, Patrick Vliex, André Zambanini, and Stefan Van Waasen · en
Source: heichips.github.io - DocumentAccess not confirmedSCALLOP: A Scalable CryoCMOS DAC Array in IHP 130nm BiCMOS for Flux-Bias Control of Superconducting Qubits
Luis E. Ardila-Perez, Lukas Scheller · en
Source: heichips.github.io - DocumentAccess not confirmedReconfigurable processing units inside RISC-V cores
Philippos Papaphilippou · en
Source: heichips.github.io - DocumentAccess not confirmedUnpredictable by Design: Race Hazard & Jitter-Enhanced TRNG with Braided Logic Gates on FPGA
Hossam O. Ahmed · en
Source: heichips.github.io
Materials checked:
The school combined analogue and digital chip design, CIRCT and LibreLane workshops, posters and a team hackathon. FPGA-related projects included eFPGA integration, a sorter and FPGA-based hardware validation.