Results
Best Project Award (shared): FazyRV-ExoTiny CCX. Team: Meinhard Kissich, Matthias Musch, Sabih Muhammad, Spandan Das, Marcin Kowalczyk.
Source: heichips.github.ioBest Project Award (shared): Waveform + Tone Generation using CORDIC Algorithm. Team: Shankaranarayanan H, Naveen Dhage Shankar, Guha H, Ketan Sanjay Chaudhari.
Source: heichips.github.io
Materials
64 found
- DocumentAccess not confirmedFPGA Ray Marching: 3D CORDIC for Extreme Mandelbulb Precision
Kevin Klein · en
Source: heichips.github.io - Source codeAccess not confirmedHeiChips 2025: combined tapeout designs
Krzysztof Herman · en
Source: heichips.github.io - Source codeAccess not confirmedbAG O' Life
en
Source: heichips.github.io - SlidesAccess not confirmedbAG O' Life
en
Source: heichips.github.io - Source codeAccess not confirmedUSB Core
en
Source: heichips.github.io - SlidesAccess not confirmedUSB Core
en
Source: heichips.github.io - Source codeAccess not confirmedSoftware Defined Radio Accelerator
en
Source: heichips.github.io - SlidesAccess not confirmedSoftware Defined Radio Accelerator
en
Source: heichips.github.io - Source codeAccess not confirmedPUDDING (Public Use DAC for Icy Nano-ampere current Generation)
en
Source: heichips.github.io - Source codeAccess not confirmed8 bit CPU + eFPGA/sorter
en
Source: heichips.github.io - SlidesAccess not confirmed8 bit CPU + eFPGA/sorter
en
Source: heichips.github.io - Source codeAccess not confirmedFazyRV-ExoTiny CCX
en
Source: heichips.github.io - SlidesAccess not confirmedFazyRV-ExoTiny CCX
en
Source: heichips.github.io - Source codeAccess not confirmedTiny systolic array
en
Source: heichips.github.io - SlidesAccess not confirmedTiny systolic array
en
Source: heichips.github.io - Source codeAccess not confirmedWaveform + Tone Generation using CORDIC Algorithm
en
Source: heichips.github.io - SlidesAccess not confirmedWaveform + Tone Generation using CORDIC Algorithm
en
Source: heichips.github.io - Source codeAccess not confirmedSnitch (32b RISC-V Integer Core)
en
Source: heichips.github.io - SlidesAccess not confirmedSnitch (32b RISC-V Integer Core)
en
Source: heichips.github.io - Source codeAccess not confirmedFancy ALU (FALU)
en
Source: heichips.github.io
Materials checked:
The school combined analogue and digital chip design, CIRCT and LibreLane workshops, posters and a team hackathon. FPGA-related projects included eFPGA integration, a sorter and FPGA-based hardware validation.