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FPGA-Systems 2025 with YADRO — Moscow

HybridCompleted
Verilog / SystemVerilogFPGA + SoCEducationOpen-source

Recordings from both rooms of the 29 November 2025 conference: RTL, DSP, PCIe prototyping, FPGA-to-ASIC design, verification and physical implementation.

FPGA community illustration from the YADRO event website
Image: YADRO. Official source.

Programme

Two parallel tracks covered RTL, signal processing, prototyping, verification, physical design and education. Topics included PCIe on AMD/Xilinx, SpinalHDL, FIR filters, DFT, Simtera IC and RTL learning platforms.

Arrival started at 10:00, with the shared programme at 11:00. Talks ended at 18:30; networking and exhibits continued until 21:00. The conference ran in Moscow and online.

Recordings and slides

Recording: room 1

Recording: room 2

Using the materials

Recordings are split by room. Match a talk to the official programme to choose the right track; old registration forms refer to the completed conference.

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