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FPGA-Systems

FPGA developer community holding events on RTL, verification, signal processing and design tools.

Related news

YADRO FPGA event coverageNoteOctober 8, 2026

YADRO: FPGA-Systems and SoC Design Challenge archive

Recordings from six FPGA-Systems events, five SoC Design Challenge editions and an FPGA workshop, plus application deadlines for the 2026/27 synthesis…

Verilog / SystemVerilog FPGA + SoC Education

YADRO FPGA event coverageNoteOctober 8, 2026

YADRO and FPGA-Systems meet in Nizhny Novgorod on 14 November

14 November at Lobachevsky University and online: RISC-V modelling, SoC benchmarking on FPGA, FFT architectures, JTAG, Verihogg and FPGA optimisation.

Verilog / SystemVerilog FPGA + SoC RISC-V

Upcoming activity

May 25, 2024, 11:00–17:00 Russia · Saint PetersburgCompleted

FPGA-Systems 2024.1 with YADRO — Saint Petersburg

Recording and slides from 25 May 2024: a DDC/DUC transceiver, verification strategy, trusted boot, PyUVM and reusable RTL verification components.

Hybrid Verilog / SystemVerilog FPGA + SoC

Jun 1, 2024, 11:00–17:00 Russia · MoscowCompleted

FPGA-Systems 2024.1 with YADRO — Moscow

Recording and slides from the 1 June 2024 conference: SATA on FPGA, AVC/H.264, industrial automation, Simtera and RISC-V.

Hybrid Verilog / SystemVerilog FPGA + SoC

Oct 26, 2024, 11:00–18:00 Russia · Saint PetersburgCompleted

FPGA-Systems 2024.02 × YADRO — Saint Petersburg

Recording and slides from 26 October 2024: FPGA and ASIC physical design, embedded Linux, prototyping, PyUVM and Simtera.

Hybrid Verilog / SystemVerilog FPGA + SoC

Nov 30, 2024, 10:30–18:00 Russia · MoscowCompleted

FPGA-Systems 2024.02 × YADRO — Moscow

Programme, recording and slides from 30 November 2024: Chisel/Scala, UVM, RISC-V, verification, timing and HDMI on FPGA.

Hybrid Verilog / SystemVerilog FPGA + SoC