
Programme and recording
FPGA-Systems held the conference in Saint Petersburg with an online stream. YADRO supported it as a partner.
Separate recording chapters cover SystemVerilog event regions and the move from OpenCL to Intel oneAPI for high-level synthesis.
Recording with programme and timestamps
SystemVerilog event regions — 13:54
From OpenCL to Intel oneAPI — 6:03:35
Archive
Date and materials checked on 8 October 2026.