FPGA-Systems 2024.1 with YADRO — Saint Petersburg

Programme

Talks covered an amateur-radio DDC/DUC transceiver, verification strategy, FPGA development mistakes, trusted OS boot, PyUVM and a library of RTL verification components.

The YADRO-supported FPGA-Systems conference ran on 25 May from 11:00 to 17:00 at PetroCongress and online.

Recordings and slides

Event recording

Portable DDC/DUC radio transceiver

Building a verification strategy

PyUVM framework overview

Reusable verification components

Using the materials

For verification planning, start with the strategy talk, then compare PyUVM and the component-library approach. The event has ended; the recording and slides remain available.