FPGA-Systems 2024.02 × YADRO — Saint Petersburg

Programme

Talks covered FPGA and ASIC physical design, FPGA use in research, embedded Linux on Xilinx Zynq, a RISC-V SoC with programmable logic, ASIC prototyping, PyUVM and Simtera.

The main programme ran from 11:00 to 18:00, with exhibits opening at 10:30. The YADRO-supported meetup took place at PetroCongress and online.

Recordings and slides

Event recording

Physical design: FPGA versus ASIC

Embedded Linux on Xilinx Zynq

PyUVM for FPGA verification

Using Simtera for simulation and synthesis

Using the materials

The physical-design slides compare FPGA and ASIC flows. Separate PyUVM and Simtera materials cover RTL verification.