100G Ethernet on FPGA: buy IP or build an open-source stack

Overview

Why this comparison now. On 30 September 2026 Orthogone Technologies announced an IP kit with Ethernet MAC/PCS up to 100G, TCP/IP and UDP/IP offload engines and a PCIe DMA controller, delivered as encrypted RTL. For a team that needs 100G Ethernet on an FPGA this reopens an old question: pay for closed IP or assemble an open stack. This text compares published claims; the editorial team has made no measurements, and every number below is the vendor's or the project's own. Editorial conclusions are marked as such.

The candidates. Commercial: Orthogone ULL IP (encrypted RTL, per-project to per-card licences). Vendor hard block: the AMD UltraScale+ integrated 100G Ethernet subsystem (CMAC, PG203). Open source: taxi (the successor of verilog-ethernet and the home of Corundum), the deprecated verilog-ethernet (site card /cores/verilog-ethernet), LiteEth (/cores/liteeth), and the Corundum NIC platform. The site cards /cores/taxi and /cores/litepcie are useful companions for the offload and DMA parts.

Licence and openness. Orthogone delivers encrypted RTL under a commercial licence, so the source cannot be audited or modified. AMD CMAC is a hard block provided at no additional cost with Vivado under the End User License, with a no-charge licence key; only the optional soft auto-negotiation and link training is licensed separately. taxi is dual-licensed: CERN-OHL-S-2.0 (strongly reciprocal: the source of the whole design must be provided on request) or a paid commercial licence. verilog-ethernet is MIT, LiteEth is BSD 2-clause and explicitly allows closed-source designs. Corundum has a LICENSE file that GitHub does not classify with an SPDX identifier, so read the file before use. Editorial inference: for a product with a closed bitstream, CERN-OHL-S is the licence that most needs a lawyer.

Supported speeds. Orthogone lists 1G, 10G, 25G, 40G and 100G, with optional RS-FEC at 25G and 100G. AMD CMAC covers 100G on UltraScale+ (CAUI-10, CAUI-4, 100GAUI-2/4); a hard block means no 10G or 25G in the same block. taxi has MAC and PCS up to 25G in soft logic and wraps the hard CMAC for 100G only. verilog-ethernet reaches 10G and 25G. LiteEth lists PHYs up to 25GBASE-R on selected Xilinx devices; 100G is not listed. Corundum targets 10G/25G/100G, with 100G on UltraScale+ through the CMAC. Editorial inference: if you need 100G on a non-UltraScale+ device, the published sources point to the commercial option; this should be confirmed with the vendor, since the Orthogone press release names only AMD UltraScale+ and Versal.

Protocol offload. Orthogone offers TCP/IP and UDP/IP offload for layers 2 to 4, with up to 64 connections per endpoint, on its 10G product page. taxi includes the Zircon stack with IPv4, IPv6 and UDP from 1G to 100G, and marks TCP and RDMA as planned. verilog-ethernet has a UDP/IP/ARP stack at gigabit and 10G/25G. LiteEth provides ARP, ICMP, UDP and DHCP. CMAC is a MAC/PCS block and has no protocol stack. Editorial inference: among the sources checked, hardware TCP is documented only for Orthogone; a team that needs TCP in fabric should check whether TCP over the host stack would be enough before paying for it.

DMA and drivers. Orthogone ships a Linux driver stack and a kernel-bypass DMA design with a kernel module in rpm and deb packages. Corundum has a custom PCIe DMA engine, a Linux driver and a simulation framework that models the host side; taxi describes DPDK support for the next-generation version and warns it may not be ready for production. CMAC has no software driver (the IP facts list none) and no DMA. LiteEth lists a DMA interface to the MAC as a possible improvement; for PCIe the site card /cores/litepcie covers that part. Editorial inference: the DMA and driver layer is where open and closed options differ most in integration effort.

Verification. Orthogone states that its cores are verified with a UVM environment and tested for interoperability against network test equipment; this is a vendor statement and testbenches are included in the kit. AMD provides a Verilog example design and test bench with CMAC. taxi and verilog-ethernet use cocotb testbenches; taxi also uses Verilator. LiteEth ships unit tests. Corundum documents a full-system simulation framework. None of these claims replaces your own regression; the useful question is which testbench you can run on your own simulator and with your own traffic.

Support and cost of ownership. No source publishes prices, so none are given here. Cost components can still be listed. Orthogone: licence (project, site, corporate, annualised or per-card), the engineering time for integration, and vendor support; the vendor says on its FAQ that it can provide technical support and maintenance for solutions it develops, and offers a free 30-day evaluation. AMD CMAC: no extra IP licence fee with Vivado, and an optional paid auto-negotiation and link-training core. taxi: either source-sharing duties or a paid commercial licence, plus commercial support from the maintainers. verilog-ethernet: no maintenance; the README redirects to taxi. LiteEth: BSD licence, with commercial support and consulting offered by EnjoyDigital. Corundum: open, but the taxi README says Corundum is under active development and may not be ready for production.

Reading vendor numbers. Orthogone publishes 17.1 ns round trip for 10G MAC/PCS (16-bit paths, GTY plus MAC/PCS, TxSoP to RxSoF in serial loopback) and 34.1 ns when a clock domain crossing and a 32-bit interface are included; for 100G on UltraScale+ it lists 196 ns without and 399 ns with RS-FEC. taxi publishes resource and timing-closure statements for its 10G/25G MAC and PCS on specific boards instead of latency. These figures answer different questions and cannot be put in one table. That is why a reader needs a protocol.

Measurement protocol for the reader (a proposal, not a result). First, fix the platform: one device, speed grade and tool version for all candidates, and the same transceiver wrapper settings. Second, MAC-to-MAC latency: use two ports on one board or two boards, define the timestamp points (first bit of Tx at the user interface to first bit at the Rx user interface, or SoP to SoF) and keep them the same for every candidate; report RS-FEC on and off, with and without clock domain crossing; measure at 64-byte and at jumbo frames; report minimum, median and high percentiles, not just the minimum. Third, resources: after implementation, record LUT, FF, BRAM and URAM with statistics counters on and off, for the MAC/PCS only and for the full path including transceiver wrapper. Fourth, timing margin: record worst negative slack at the target clock over several placement seeds. Fifth, correctness: line rate at 64-byte frames without loss, mixed traffic, FCS errors, pause frames, and for offload engines packet loss and reordering.

Where each option fits (editorial hypotheses, to be checked by the protocol above). A team that needs only a 100G MAC on UltraScale+ should look at CMAC first, since the published terms add no IP fee and the block is hard. A team that needs 10G or 25G with source access for audit and has no sharing restriction can start from taxi, and if the product is closed, check the CERN-OHL-S terms or the commercial licence. A team that needs TCP offload and a ready kernel-bypass path on AMD cards is the target of the Orthogone kit, with the trade-off of encrypted RTL. Corundum is a platform for NIC work rather than a MAC drop-in; verilog-ethernet is best treated as a reference.

Limits of this text. Prices and independent benchmarks were not found. The AMD documentation portal renders pages with scripts; the PG203 sections cited here were read through the portal's own content API and cited by their reader URLs. The Orthogone product pages mention supported platforms beyond AMD in one table, while the press release names only AMD UltraScale+ and Versal.

Verified facts

verilog-ethernet README states the repository is deprecated and superseded by taxi. Source: https://github.com/alexforencich/verilog-ethernet. Checked: 2026-10-02. Confidence: 5/5.

taxi is under CERN-OHL-S-2.0 or a paid commercial licence. Source: https://github.com/fpganinja/taxi. Checked: 2026-10-02. Confidence: 5/5.

LiteEth is BSD 2-clause licensed. Source: https://github.com/enjoy-digital/liteeth. Checked: 2026-10-02. Confidence: 5/5.

Orthogone delivers encrypted RTL with five licensing options and no published prices. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02. Confidence: 5/5.

AMD CMAC is provided at no additional cost with Vivado, with optional separately licensed AN/LT. Source: https://docs.amd.com/r/en-US/pg203-cmac-usplus/Licensing-and-Ordering. Checked: 2026-10-02. Confidence: 5/5.

Corundum uses verilog-ethernet MAC/PHY at 10G/25G and the CMAC with RS-FEC at 100G on UltraScale+. Source: https://github.com/corundum/corundum. Checked: 2026-10-02. Confidence: 5/5.

Engineering benefit

A reader gets a criteria list and a measurement protocol (latency with defined timestamp points, resources, timing margin over seeds) that makes vendor figures comparable. Protocol is an editorial proposal; the editorial team ran no measurements. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02. Confidence: 4/5.

The AMD hard CMAC provides 100G Ethernet on UltraScale+ at no extra IP licence cost with Vivado, which removes soft-logic resources for the MAC. Source: https://docs.amd.com/r/en-US/pg203-cmac-usplus/Licensing-and-Ordering. Checked: 2026-10-02. Confidence: 5/5.

Commercial benefit

The licence matrix shows the cost drivers without prices: Orthogone per-project to per-card licences, taxi source-sharing or paid commercial licence, CMAC free with Vivado, LiteEth BSD. No price is published by any source. Source: https://github.com/fpganinja/taxi. Checked: 2026-10-02. Confidence: 4/5.

Community benefit

Open projects (taxi, verilog-ethernet, LiteEth, Corundum) publish source, tests and documentation that the community can reuse; the deprecation notice of verilog-ethernet tells users where maintenance moved. Source: https://github.com/alexforencich/verilog-ethernet. Checked: 2026-10-02. Confidence: 4/5.

Critical review

The comparison mixes a commercial kit, a vendor hard block and community projects of very different scope; a table of ticks could suggest equivalence that does not exist. Source: https://github.com/fpganinja/taxi. Checked: 2026-10-02. Confidence: 4/5.

All numbers are vendor or project claims under their own conditions; Orthogone figures differ by measurement point (17.1 ns versus 34.1 ns for the same 10G core). Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02. Confidence: 5/5.

The Corundum repository licence is not auto-detected by GitHub and the taxi licence is strongly reciprocal; a wrong reading of either has legal consequences for a closed product. Source: https://github.com/corundum/corundum. Checked: 2026-10-02. Confidence: 4/5.

Orthogone TCP offload and the PCIe DMA are documented mostly for 10G and for Gen4 x8; applying them to a 100G design is an extrapolation. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/high-speed-data-transfer-smartnics-host-cpu-pcie-dma-controller/. Checked: 2026-10-02. Confidence: 4/5.

Defining criteria and a measurement protocol, rather than a ranking, avoids claiming a winner without data. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02. Confidence: 4/5.

Primary sources for each option (READMEs, product pages, PG203 sections, press release) are cited and dated. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02. Confidence: 5/5.

Practical recommendations

Before a purchase decision, ask each vendor or project for the same three things: the timestamp points of the latency figure, the device and speed grade, and the testbench that produced it. A latency number without its measurement points is a very short story.

Build the comparison on one board and keep the scripts in git; the third reproduction of a result is usually where the spreadsheet stops arguing.

Official links

Orthogone press release

Orthogone ULL Ethernet MAC/PCS

Orthogone TCP/UDP/IP offload

Orthogone PCIe DMA

verilog-ethernet (GitHub)

taxi (GitHub)

LiteEth (GitHub)

Corundum (GitHub)

AMD PG203: features

AMD PG203: licensing and ordering

AMD PG203: IP facts

Evidence

Orthogone ULL IP Portfolio (30 Sep 2026): Ethernet MAC/PCS 1G-100G with optional RS-FEC at 25G and 100G, TCP/IP and UDP/IP offload engines, PCIe circular-buffer DMA; encrypted RTL, Alveo reference designs, simulation testbenches, Linux driver stack; project, site, corporate, annualized and per-card licences; AMD UltraScale+ and Versal. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02.

Orthogone product pages publish latency, LUT/FF/BRAM and clock figures with conditions; verification is described as UVM-based (vendor statement) and a free 30-day evaluation is offered. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02.

Orthogone TCP/UDP offload: layers 2-4 (ARP, IPv4, ICMP, TCP, UDP), up to 64 connections per endpoint. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/10g-tcp-udp-ip-core/. Checked: 2026-10-02.

Orthogone PCIe DMA: kernel-bypass Linux driver (rpm/deb kernel module, library API); minimum round trip 585 ns under stated conditions (Gen4 x8, AMD x3522pv). Source: https://orthogone.com/ultra-low-latency-ethernet-mac/high-speed-data-transfer-smartnics-host-cpu-pcie-dma-controller/. Checked: 2026-10-02.

verilog-ethernet is MIT licensed and its README carries a deprecation notice: superseded by taxi, no future maintenance or support; commercial support is available via taxi. Source: https://github.com/alexforencich/verilog-ethernet. Checked: 2026-10-02.

verilog-ethernet covers gigabit, 10G and 25G MAC/PCS/PMA, a UDP/IP/ARP stack, PTP components and cocotb testbenches. Source: https://github.com/alexforencich/verilog-ethernet. Checked: 2026-10-02.

taxi is offered under CERN-OHL-S-2.0 or a paid commercial licence; strongly reciprocal terms require sharing the source of the whole design on request; contributions need a CLA. Source: https://github.com/fpganinja/taxi. Checked: 2026-10-02.

taxi has MAC/PCS variants from 10 Mbps to 25 Gbps, a wrapper for the UltraScale/UltraScale+ hard CMAC at 100 Gbps, the Zircon IPv4/IPv6/UDP stack (TCP, RDMA planned) and the Corundum NIC; Corundum and Zircon are marked as not necessarily ready for production; tests use cocotb and Verilator. Source: https://github.com/fpganinja/taxi. Checked: 2026-10-02.

LiteEth is BSD 2-clause licensed, supports MII to 25GBASE-R PHYs on selected Xilinx devices, ARP/ICMP/UDP/DHCP and Etherbone; a DMA interface to the MAC and standard AXI/Avalon-ST interfaces are listed as possible improvements; unit tests are in ./test. Source: https://github.com/enjoy-digital/liteeth. Checked: 2026-10-02.

Corundum is an FPGA NIC platform with 10G/25G/100G Ethernet, PCIe gen 3, a custom DMA engine, a Linux driver and a simulation framework; at 10G/25G it uses MAC/PHY modules from verilog-ethernet; 100G on Xilinx UltraScale+ requires the CMAC with RS-FEC under the free CMAC licence. GitHub does not auto-detect an SPDX licence for the repository. Source: https://github.com/corundum/corundum. Checked: 2026-10-02.

AMD UltraScale+ Integrated 100G Ethernet Subsystem (PG203): CAUI-10, CAUI-4, 100GAUI-2/4, 512-bit LBUS/AXI4-Stream at about 322 MHz, IEEE 1588 timestamping, pause and PFC, optional built-in RS-FEC in CAUI-4. Source: https://docs.amd.com/r/en-US/pg203-cmac-usplus/Features. Checked: 2026-10-02.

PG203: module provided at no additional cost with Vivado under the End User License, with a no-charge licence key; optional soft AN/LT is licensed separately; the IP facts table lists Verilog design files, example design and test bench, and no supported software driver. (IP Facts: https://docs.amd.com/r/en-US/pg203-cmac-usplus/IP-Facts) Source: https://docs.amd.com/r/en-US/pg203-cmac-usplus/Licensing-and-Ordering. Checked: 2026-10-02.