64-bit soft CPU on FPGA: Sapphire RV64 and alternatives

Summary

Comparison of Efinix Sapphire RV64 with MicroBlaze V, Nios V, VexiiRiscv and NEORV32 from official sources, with editorial conclusions on soft CPU versus hard SoC.

Overview

On 28 September 2026 Efinix announced Sapphire RV64, a 64-bit RISC-V soft SoC for its FPGAs. The announcement raises a practical question: if you need a 64-bit processor in the fabric, what else is available, and what does each option tie you to? This article compares Sapphire RV64 with AMD MicroBlaze V, Altera Nios V, VexiiRiscv and NEORV32 using official vendor pages, repositories and documentation only. We ran none of these cores. Where a statement goes beyond the sources it is marked as an editorial conclusion.

What Efinix states

The press release describes a seven-stage pipeline implementing RISC-V64IM with optional A, F, D, C, Zba, Zbb, Zbs and Zicbom extensions and an optional SV39 memory management unit for Linux. The support page adds one to four processors, a clock configurable from 20 to 400 MHz (limited by the fMAX of the design), and DDR3, LPDDR4x or HyperRAM modules from 4 MB to 8 GB. Efinix says the core is similar to the open-source VexiiRiscv but optimized for Trion and Titanium FPGAs. Cores are configured in the Efinity IP Manager and built with Efinity, so the processor exists only for Efinix devices. Resource tables for Efinity 2026.1 show Titanium Ti375 C529 at 10,740 logic/adders, 9,024 flip-flops, 91 memory blocks, 17 DSP blocks and 271 MHz for the Basic L1 configuration, and 27,250, 17,869, 225, 17 and 252 MHz for Advanced L2; Trion T120 F324 shows 77 MHz and 65 MHz for the same two. These are vendor figures for named devices and configurations and depend on the device.

AMD MicroBlaze V

AMD describes MicroBlaze V as a soft-core RISC-V processor IP for AMD adaptive SoCs and FPGAs, integrated in Vivado and Vitis. The base ISA is configurable as RV32I or RV64I with optional M, A, F, C and bit manipulation extensions, with four pipeline options and optional dual-core lockstep and triple modular redundancy. AMD states it can target any adaptive SoC or FPGA supported by Vivado at no extra cost. A footnote says the microcontroller configuration is in Production, RV64I with a Memory Protection Unit is in Early Access, and a Memory Management Unit is on the roadmap. The text we collected does not state Linux support.

Altera Nios V

The official Altera example-design repositories describe three Nios V variants: Nios V/m, a balanced microcontroller for interrupt-driven bare-metal and RTOS code; Nios V/g, a high-performance general-purpose processor; and Nios V/c, the smallest compact microcontroller for non-interrupt-driven bare-metal code. Example designs cover Agilex 7 and Agilex 5 kits, including a Soft-SoC system and a TinyML design on Nios V/g. Altera and Intel product pages answered our automated collection with HTTP 403, so the Nios V ISA, MMU, Linux support, licence and tools are not verified in this article and are left out of the comparison on purpose.

VexiiRiscv

VexiiRiscv is the SpinalHDL project that the README calls the successor of VexRiscv; the site has the older core as /cores/vexriscv. It supports RV32/64 with optional extensions, in-order single or dual issue, an optional SV32/SV39 MMU and can run Linux, Buildroot and Debian, over AXI4, Wishbone or Tilelink. The README reports up to 5.24 CoreMark/MHz without naming a configuration. The LICENSE file is MIT; the documentation lists a Scala / SpinalHDL framework and Verilog generation, and says the core should fit all FPGA families and be portable to ASIC.

NEORV32

NEORV32 is a small, 32-bit RISC-V soft-core CPU and microcontroller-like SoC in platform-independent VHDL, BSD-3-Clause licensed (see /cores/neorv32). Its README states that it passes the official RISC-V Architectural Certification Tests, can run nommu-Linux, was synthesized for AMD, Intel, Lattice, Microchip, Gowin and Cologne Chip FPGAs and has been taped out as ASIC. It also offers a custom functions unit for custom instructions and an OpenOCD and GDB compatible debugger. It is positioned as an auxiliary controller or a tiny microcontroller, not as a 64-bit Linux processor.

Comparison by axes

Width and ISA. Sapphire RV64 is RV64IM with options, MicroBlaze V is RV32I or RV64I by configuration, VexiiRiscv is RV32/64, NEORV32 is 32-bit. MMU and Linux. Sapphire RV64 and VexiiRiscv offer an optional MMU for Linux, NEORV32 runs nommu-Linux, MicroBlaze V lists an MMU on the roadmap. Licence and binding. Sapphire RV64 and MicroBlaze V are tied to Efinix and AMD devices and tools; VexiiRiscv (MIT) and NEORV32 (BSD-3-Clause) are open source and move between vendors. Tools. Efinity, Vivado with Vitis, sbt or Docker for VexiiRiscv, and for NEORV32 RISC-V GCC for software with VHDL for the hardware.

Why a Linux-capable soft CPU when hard SoCs exist

Hard-processor FPGAs are real alternatives: AMD describes Zynq UltraScale+ MPSoCs with dual or quad application processors next to programmable logic, and the Altera Agilex 5 E-Series reference design enables a hard processor system with dual Cortex-A76 and dual Cortex-A55 cores that boots U-Boot and then Linux. Efinix itself lists a hardened RV32 SoC with a Linux MMU and a clock up to 1 GHz in selected FPGAs, against 65 to 278 MHz fMAX in the soft RV64 tables. Editorial conclusion: when your device already has a hard application processor that fits the job, it will usually be the simpler way to Linux, and spends no fabric.

Editorial conclusion: a Linux-capable soft CPU makes sense when the chosen FPGA family has no suitable hard processor, when you need a 64-bit address space inside the fabric, when you want custom instructions next to your own logic (Sapphire RV64 and NEORV32 both list this), or when you need a core you can take to another vendor or to ASIC (VexiiRiscv and NEORV32). The price is fabric area, a lower clock and your own bring-up work. The sources give no figures for Linux boot time or power, so these remain hypotheses to check.

How to measure it yourself

We have no results, so here is a protocol. Pick one device per vendor, fix the compiler flags and use the same CoreMark build for every core. Where an MMU exists, boot the same kernel configuration to a shell and record the time. Run place and route with identical clock constraints and three seeds, and record fMAX, logic, flip-flops, memory blocks and DSP blocks. Add a memory copy test over the external memory interface. Write down tool versions, core configuration and licence terms on the test day, and publish raw logs next to the table.

Verified facts

Width and ISA: Sapphire RV64 is RV64IM with optional extensions; MicroBlaze V is configurable RV32I or RV64I; VexiiRiscv is RV32/64; NEORV32 is 32-bit; the collected Nios V pages do not state the ISA. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02. Confidence: 4/5.

MMU and Linux: Sapphire RV64 offers an optional SV39 MMU for Linux; VexiiRiscv an optional SV32/SV39 MMU and Linux/Debian; NEORV32 nommu-Linux; MicroBlaze V lists an MMU on the roadmap; Nios V is not stated in the collected pages. Source: https://github.com/SpinalHDL/VexiiRiscv. Checked: 2026-10-02. Confidence: 4/5.

Licence and binding: Sapphire RV64 and MicroBlaze V run only on Efinix or AMD devices through their tools; VexiiRiscv is MIT, NEORV32 is BSD-3-Clause; Nios V terms are not collected. Source: https://raw.githubusercontent.com/stnolting/neorv32/main/LICENSE. Checked: 2026-10-02. Confidence: 4/5.

Efinix calls its core similar to VexiiRiscv; this is Efinix wording and not a statement of identical RTL. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 5/5.

Frequencies and resources: Sapphire RV64 tables are vendor figures for named devices and configurations; the 400 MHz setting is an upper bound, not a result. Depend on the device. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 5/5.

Efinix offers a hardened 1 GHz-capable RV32 SoC with a Linux MMU in selected FPGAs next to its 64-bit soft core. Source: https://www.efinixinc.com/products-riscv.html. Checked: 2026-10-02. Confidence: 4/5.

AMD and Altera publish hard-processor SoC FPGAs (Zynq UltraScale+ MPSoC; Agilex 5 E-Series HPS with Arm Cortex-A76/A55 and Linux boot in the reference design). Source: https://github.com/altera-fpga/agilex5e-ed-gsrd. Checked: 2026-10-02. Confidence: 4/5.

Engineering benefit

A reader can choose by facts: 64-bit with optional MMU (Sapphire RV64, MicroBlaze V in Early Access, VexiiRiscv) versus 32-bit and nommu (NEORV32). Vendor and project statements; not measured by us. Source: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/microblaze-v.html. Checked: 2026-10-02. Confidence: 4/5.

A measurement protocol makes the vendor claims comparable on one device instead of across different tables. Editorial proposal; no results are given. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 3/5.

Open cores (VexiiRiscv MIT, NEORV32 BSD-3-Clause) can be inspected and moved between vendors, unlike vendor IP. Source: https://raw.githubusercontent.com/stnolting/neorv32/main/LICENSE. Checked: 2026-10-02. Confidence: 4/5.

Commercial benefit

Vendor soft CPUs are bound to one device family and tool flow (Efinity for Sapphire RV64, Vivado and Vitis for MicroBlaze V); MicroBlaze V is stated to cost nothing extra with Vivado. No price or licence terms are given for Sapphire RV64. Source: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/microblaze-v.html. Checked: 2026-10-02. Confidence: 4/5.

Permissive licences (MIT, BSD-3-Clause) allow commercial reuse subject to notice requirements. Not legal advice. Source: https://raw.githubusercontent.com/SpinalHDL/VexiiRiscv/dev/LICENSE. Checked: 2026-10-02. Confidence: 4/5.

Community benefit

Public documentation, tutorials and RISC-V compliance tests (VexiiRiscv, NEORV32) let students and independent engineers study full processor designs. Source: https://github.com/stnolting/neorv32. Checked: 2026-10-02. Confidence: 4/5.

Efinix describing its core as similar to an open-source project lets the community relate vendor and open material (editorial inference). Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 3/5.

Critical review

Altera and Intel product pages for Nios V returned HTTP 403 to automated collection, so Nios V ISA, MMU, Linux, licence and tools are not verified here; only the variant descriptions in Altera example-design repositories are used. Source: https://github.com/altera-fpga/agilex7-ed-niosv. Checked: 2026-10-02. Confidence: 5/5.

The MicroBlaze V statuses (Production, Early Access, roadmap) come from a page footnote and can change; Linux support is not stated in the text we collected. Source: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/microblaze-v.html. Checked: 2026-10-02. Confidence: 4/5.

Efinix pages word the Trion device list differently (T20 and above in the press release; all except T4 or T4 and T8 on other pages). Source: https://www.efinixinc.com/products-riscv.html. Checked: 2026-10-02. Confidence: 4/5.

Numbers from different tables are not comparable: Efinix fMAX is for named devices in Efinity 2026.1, VexiiRiscv CoreMark/MHz is author-reported without a named configuration. Source: https://github.com/SpinalHDL/VexiiRiscv. Checked: 2026-10-02. Confidence: 5/5.

The hard-SoC discussion uses AMD and Altera pages only; Microchip PolarFire SoC pages were not retrievable by automated collection (HTTP 403) and are not covered. Source: https://www.amd.com/en/products/adaptive-socs-and-fpgas/soc/zynq-ultrascale-plus-mpsoc.html. Checked: 2026-10-02. Confidence: 5/5.

Where official pages are readable, they state ISA, MMU, licence and tool flow explicitly, so most comparison axes are sourced. Source: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/microblaze-v.html. Checked: 2026-10-02. Confidence: 4/5.

The article reports no measurements of its own and labels editorial conclusions. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 5/5.

Practical recommendations

Before choosing a core, write down which axis decides for you (Linux, licence, vendor, size) and discard the rest of the table.

Read each vendor figure with its device and tool version beside it; a frequency without a device is a horoscope.

Official links

Efinix press release (28 Sep 2026)

Efinix Sapphire RV64 SoC support page

Efinix RISC-V SoCs

AMD MicroBlaze V processor

Altera Nios V example designs (Agilex 7)

Altera Nios V example designs (Agilex 5)

NEORV32 repository (README)

NEORV32 data sheet

VexiiRiscv repository

VexiiRiscv documentation

AMD Zynq UltraScale+ MPSoCs

Altera Agilex 5 E-Series GSRD

Evidence

On 28 September 2026 Efinix announced the Sapphire RV64 SoC, a 64-bit RISC-V core extending its 32-bit Sapphire SoC suite. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02.

Sapphire RV64: seven-stage pipeline, RISC-V64IM with optional A, F, D, C, Zba, Zbb, Zbs and Zicbom, optional SV39 MMU for Linux. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02.

Sapphire RV64 supports one to four processors, 20 to 400 MHz configurable clock limited by design fMAX, and DDR3, LPDDR4x or HyperRAM modules from 4 MB to 8 GB. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02.

Efinix says the Sapphire RV64 core is similar to the open-source VexiiRiscv but optimized for Trion and Titanium FPGAs. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02.

Sapphire RV64 resource and fMAX tables (Efinity 2026.1): Titanium Ti375 C529 Basic L1 is 10,740 logic/adders, 9,024 flip-flops, 91 memory blocks, 17 DSP blocks, 271 MHz; Advanced L2 is 27,250, 17,869, 225, 17, 252 MHz; Trion T120 F324 Basic L1 is 77 MHz and Advanced L2 is 65 MHz. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02.

Efinix also lists a hardened High-performance Sapphire RV32 SoC: four VexRiscv processors, up to 1 GHz, FPU, Linux MMU, LPDDR4x, only in selected FPGAs. Source: https://www.efinixinc.com/products-riscv.html. Checked: 2026-10-02.

AMD MicroBlaze V is a soft-core RISC-V processor IP for AMD adaptive SoCs and FPGAs, integrated in Vivado and Vitis, with configurable RV32I and RV64I base ISA and optional M, A, F, C and bit manipulation extensions. Source: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/microblaze-v.html. Checked: 2026-10-02.

AMD states MicroBlaze V can target any AMD adaptive SoC or FPGA supported by Vivado at no extra cost, offers four pipeline options and optional dual-core lockstep and triple modular redundancy. Source: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/microblaze-v.html. Checked: 2026-10-02.

AMD footnote on the MicroBlaze V page: the microcontroller configuration is in Production, RV64I with Memory Protection Unit is in Early Access, and a Memory Management Unit is on the roadmap. Source: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/microblaze-v.html. Checked: 2026-10-02.

Altera example-design repositories describe three Nios V variants: Nios V/m (microcontroller, balanced), Nios V/g (general-purpose processor, high performance) and Nios V/c (compact microcontroller, smallest). Source: https://github.com/altera-fpga/agilex7-ed-niosv. Checked: 2026-10-02.

Nios V example designs exist for Agilex 7 and Agilex 5 development kits, including a Soft-SoC System Example Design and a TinyML LiteRT design with Nios V/g. Source: https://github.com/altera-fpga/agilex7-ed-niosv. Checked: 2026-10-02.

Altera Agilex 5 Nios V example designs are published in a repository for Agilex 5 development kits. Source: https://github.com/altera-fpga/agilex5-ed-niosv. Checked: 2026-10-02.

NEORV32 is a small, customizable 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. Source: https://github.com/stnolting/neorv32. Checked: 2026-10-02.

NEORV32 is BSD-3-Clause licensed, passes the official RISC-V Architectural Certification Tests, is capable of running nommu-Linux, and was synthesized for AMD, Intel, Lattice, Microchip, Gowin and Cologne Chip FPGAs and taped out as ASIC. Source: https://github.com/stnolting/neorv32. Checked: 2026-10-02.

The NEORV32 LICENSE file is the BSD 3-Clause License, Copyright (c) 2020-2026 Stephan Nolting and NEORV32 contributors. Source: https://raw.githubusercontent.com/stnolting/neorv32/main/LICENSE. Checked: 2026-10-02.

The NEORV32 data sheet describes a custom functions unit (CFU), an OpenOCD and GDB compatible on-chip debugger and RISC-V GCC as the default toolchain. Source: https://stnolting.github.io/neorv32/. Checked: 2026-10-02.

VexiiRiscv: RV32/64, in-order single or dual issue, optional SV32/SV39 MMU, can run Linux, Buildroot and Debian, buses AXI4, Wishbone and Tilelink, README-reported up to 5.24 CoreMark/MHz. Source: https://github.com/SpinalHDL/VexiiRiscv. Checked: 2026-10-02.

VexiiRiscv LICENSE is the MIT License (Copyright (c) 2023 SpinalHDL); the documentation describes it as free and open-source and portable to ASIC. Source: https://raw.githubusercontent.com/SpinalHDL/VexiiRiscv/dev/LICENSE. Checked: 2026-10-02.

VexiiRiscv documentation lists a Scala / SpinalHDL framework section and a Generate verilog section; the documentation site redirects to the master version. Source: https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/Introduction/index.html. Checked: 2026-10-02.

AMD describes Zynq UltraScale+ MPSoCs as providing 64-bit processor scalability with dual application processor (CG), quad application processor and GPU (EG) and video codec (EV) variants combined with programmable logic. Source: https://www.amd.com/en/products/adaptive-socs-and-fpgas/soc/zynq-ultrascale-plus-mpsoc.html. Checked: 2026-10-02.

The Altera Agilex 5 E-Series GSRD enables a Hard Processor System with dual-core Arm Cortex-A76 and dual-core Arm Cortex-A55 processors and exercises soft IP in the fabric, boots to U-Boot, then Linux. Source: https://github.com/altera-fpga/agilex5e-ed-gsrd. Checked: 2026-10-02.