Field-programmable gate array: configurable digital logic fabric programmed after manufacturing.

Programmable logic device usually smaller and more deterministic than an FPGA.

Look-up table used as a basic FPGA logic element.

Sequential storage element usually clocked by a clock edge.

Dedicated block memory inside FPGA fabric.

Dedicated arithmetic block for operations such as multiplication and accumulation.

Clock management block used to generate or condition clocks.

Configuration data loaded into an FPGA to realize a design.

Conversion of HDL into a gate-level or technology-mapped representation.

Mapping logic to physical locations and routing signals between them.

Timing analysis that checks paths against constraints without dynamic simulation.

Timing margin between required and actual path timing.

Clock domain crossing; transfer of signals between different clock domains.

Unstable state of a sequential element when setup or hold assumptions are violated.

File describing pin assignments, clocks, I/O standards and timing constraints.

AMD/Xilinx Design Constraints format used by Vivado.

Synopsys Design Constraints format used by multiple FPGA tools.

Physical constraints format commonly seen in open iCE40 flows.

Quartus Settings File used in Intel FPGA projects.

Constraint format used in Gowin FPGA projects.

Small expansion connector ecosystem popular on educational FPGA boards.

FPGA Mezzanine Card connector standard for expansion modules.

Debug and programming interface used by many FPGA boards.

Asynchronous serial interface often used for simple board debug.

Synchronous serial interface commonly used for flash and peripheral chips.

Two-wire serial bus often used for low-speed control devices.

AMBA interconnect protocol family widely used in SoC FPGA designs.

Open interconnect bus used in many open-source FPGA SoC projects.

Processor implemented in FPGA fabric rather than as hardened silicon.

Retrieval-augmented generation; answering with retrieved source-backed context.