Open-source FPGA projects

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Maintainedgithub.comMay 8, 2026Apache-2.0

Suite of SystemVerilog developer tools: parser, formatter, linter, and syntax tooling.

SystemVerilogLintFormatterParserOpen-sourceVerilog / SystemVerilog

This catalog has few published projects. Only real records with a repository or verifiable source are shown; unverified projects are not created.

Repository URLLicense and statusMaintainer or source evidenceFPGA/RTL/tooling scope