Verible
Suite of SystemVerilog developer tools: parser, formatter, linter, and syntax tooling.
Verible matters to FPGA.camp as a practical SystemVerilog tooling layer: lint, format, and syntax parsing help keep RTL review and CI more repeatable.
The official Verible documentation shows a generated build from 2026-03-13 and lists verible-verilog-lint, verible-verilog-format, and verible-verilog-syntax.
Source: https://chipsalliance.github.io/verible/. Checked by FPGA.camp on 2026-05-08.