Open-source FPGA projects

3 results

Search: VerilogTopic: Open-sourceClear filters

Maintainedgithub.comMay 8, 2026Apache-2.0

Suite of SystemVerilog developer tools: parser, formatter, linter, and syntax tooling.

SystemVerilogLintFormatterParserOpen-sourceVerilog / SystemVerilog

Maintainedgithub.comApril 26, 2026LGPL-3.0 / Artistic-2.0

Open-source SystemVerilog simulator and lint system.

SystemVerilogC++SystemCLintOpen-sourceVerilator+1

Maintainedgithub.comApril 26, 2026ISC

Open SYnthesis Suite for Verilog RTL synthesis and formal-related flows.

VerilogRTLILSynthesisFormalOpen-sourceYosys+1

This catalog has few published projects. Only real records with a repository or verifiable source are shown; unverified projects are not created.

Repository URLLicense and statusMaintainer or source evidenceFPGA/RTL/tooling scope