Ibex
Checked on GitHubSmall open RISC-V CPU used by OpenTitan.
CPUs and computeSystemVerilogApache-2.0M2 · Simulation-testedupdated 2 days ago
21 cores. Check the license and tests before integration.
Small open RISC-V CPU used by OpenTitan.
CPUs and computeSystemVerilogApache-2.0M2 · Simulation-testedupdated 2 days ago
Tiny RISC-V core and FuseSoC-friendly ecosystem.
CPUs and computeVerilogISCM4 · Production-readyupdated 33 days ago
Well-documented VHDL RISC-V SoC candidate.
CPUs and computeVHDLBSD-3-ClauseM4 · Production-readyupdated today
Configurable RISC-V softcore used in LiteX ecosystem.
CPUs and computeSpinalHDL/Scala/VerilogMITM2 · Simulation-testedupdated 3 days ago
Compact softcore with strong FPGA relevance.
CPUs and computeVerilogISCM2 · Simulation-testedupdated 20 days agoarchived
Open RISC-V processor cores.
CPUs and computeSystemVerilogSolderpadM1 · Prototypeupdated 6 months ago
CPU, Wishbone and formal-heavy ecosystem.
CPUs and computeVerilogNo license foundM1 · Prototype
Linux-capable RISC-V core lineage.
CPUs and computeSystemVerilogNo license foundM1 · Prototype
Open RISC-V core family for comparison.
CPUs and computeSystemVerilogNo license foundM1 · Prototype
Floating-point arithmetic core family.
CPUs and computeNo license foundM1 · Prototype
Manycore RISC-V candidate.
CPUs and computeNo license foundM1 · Prototype
High-end RISC-V research core.
CPUs and computeNo license foundM1 · Prototype
Specific CORE-V core with verification evidence.
CPUs and computeSystemVerilogNo license foundM1 · Prototype
Security-oriented CORE-V core variant.
CPUs and computeNo license foundM1 · Prototype
CORE-V core variant.
CPUs and computeNo license foundM1 · Prototype
Important Chisel generator ecosystem.
CPUs and computeNo license foundM1 · Prototype
SoC integration candidate.
CPUs and computeNo license foundM1 · Prototype
RISC-V core comparison source.
CPUs and computeNo license foundM1 · Prototype
Historical open soft CPU baseline.
CPUs and computeVerilogNo license foundM1 · Prototype
OpenRISC core relevant to Wishbone history.
CPUs and computeVerilogNo license foundM1 · Prototype
Historical SoC integration reference.
CPUs and computeVerilog/VHDL unknown until reviewNo license foundM1 · Prototype