OpenCores UART16550
M1-M3 candidateCanonical UART reference and common FuseSoC adaptations.
opencoresAuto indexedunknown until checked
The license requires manual review.
The source appears stale or legacy.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Canonical UART reference and common FuseSoC adaptations.
The license requires manual review.
The source appears stale or legacy.
Small open RISC-V CPU used by OpenTitan.
Manual review is required.
| Signal | OpenCores UART16550 | Ibex |
|---|---|---|
| Category / source | peripheral/UART opencores | processor/RISC-V github |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M7 candidate |
| License | unknown until checkedManual review required | Apache-2.0Manual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: YesFuseSoC: YesBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | UARTunknown | unknownunknown |
| Toolchains | FuseSoC, Verilator | Verilator |
| Warnings |
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