Cores

Open HDL cores for FPGA. License, tests and activity checked on GitHub.

Category: CPUs and compute Clear filters

23 results

VexiiRiscv

Checked on GitHub

MIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.

CPUs and computeSpinalHDL (Scala)MITM2 · Simulation-testedupdated 4 days ago

Ibex

Checked on GitHub

Small open RISC-V CPU used by OpenTitan.

CPUs and computeSystemVerilogApache-2.0M2 · Simulation-testedupdated 7 days ago

BlackParrot

Checked on GitHub

Manycore RISC-V candidate.

CPUs and computeBSD-3-ClauseM2 · Simulation-testedupdated 1 day ago

SERV

Checked on GitHub

Tiny RISC-V core and FuseSoC-friendly ecosystem.

CPUs and computeVerilogISCM4 · Production-readyupdated 38 days ago

NEORV32

Checked on GitHub

Well-documented VHDL RISC-V SoC candidate.

CPUs and computeVHDLBSD-3-ClauseM4 · Production-readyupdated 5 days ago

VexRiscv

Checked on GitHub

Configurable RISC-V softcore used in LiteX ecosystem.

CPUs and computeSpinalHDL/Scala/VerilogMITM2 · Simulation-testedupdated 4 days ago

PicoRV32

Checked on GitHub

Compact softcore with strong FPGA relevance.

CPUs and computeVerilogISCM2 · Simulation-testedupdated 25 days agoarchived

ultraembedded riscv

Checked on GitHub

RISC-V core comparison source.

CPUs and computeBSD-3-ClauseM2 · Simulation-testedupdated 5 years ago

BOOM

Checked on GitHub

High-end RISC-V research core.

CPUs and computeBSD-3-ClauseM1 · Prototypeupdated 21 days ago

OpenHW CORE-V cores

Checked on GitHub

Open RISC-V processor cores.

CPUs and computeSystemVerilogSolderpadM1 · Prototypeupdated 6 months ago

OpenHW CVA6

Checked on GitHub

Linux-capable RISC-V core lineage.

CPUs and computeSystemVerilogNo license foundM4 · Production-readyupdated 4 days ago

OpenHW CV32E40P

Checked on GitHub

Specific CORE-V core with verification evidence.

CPUs and computeSystemVerilogNo license foundM4 · Production-readyupdated 1 day ago

ultraembedded core_soc

Checked on GitHub

SoC integration candidate.

CPUs and computeGPL-2.0M1 · Prototypeupdated 6 years ago

OpenRISC mor1kx

Checked on GitHub

OpenRISC core relevant to Wishbone history.

CPUs and computeVerilogNo license foundM4 · Production-readyupdated 4 months ago

ZipCPU

Checked on GitHub

CPU, Wishbone and formal-heavy ecosystem.

CPUs and computeVerilogNo license foundM2 · Simulation-testedupdated 16 days ago

Wally RISC-V

Checked on GitHub

Open RISC-V core family for comparison.

CPUs and computeSystemVerilogNo license foundM4 · Production-readyupdated 8 days ago

Berkeley HardFloat

Checked on GitHub

Floating-point arithmetic core family.

CPUs and computeNo license foundM2 · Simulation-testedupdated 44 days ago

Rocket Chip

Checked on GitHub

Important Chisel generator ecosystem.

CPUs and computeNo license foundM1 · Prototypeupdated 19 days ago

Efinix Sapphire RV64 SoC

Configurable soft RISC-V SoC from Efinix: 1 to 4 64-bit cores, optional SV39 MMU, L1 and L2 caches, DDR3, LPDDR4x and HyperRAM controller for Efinix FPGAs; licence not stated.

CPUs and computeNo license foundM1 · Prototype

OpenHW CV32E40S

Checked on GitHub

Security-oriented CORE-V core variant.

CPUs and computeNo license foundM2 · Simulation-testedupdated 2 years ago

OpenHW CV32E40X

Checked on GitHub

CORE-V core variant.

CPUs and computeNo license foundM2 · Simulation-testedupdated 2 years ago

OpenRISC or1200

Checked on GitHub

Historical open soft CPU baseline.

CPUs and computeVerilogNo license foundM2 · Simulation-testedupdated 11 years ago

opencores minsoc

Historical SoC integration reference.

CPUs and computeVerilog/VHDL unknown until reviewNo license foundM1 · Prototype