Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| opencores usbhostslave Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |
Submit a core
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
| Core | Maturity | License | Language | Activity |
|---|---|---|---|---|
| opencores usbhostslave Interfaces and peripherals | M1 · Prototype | No license found | Verilog/VHDL unknown until review | — |