KB article
What is an IP core?
What is an IP core? guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB cores
Core knowledge base
Compact KB pages for /cores users: how to read cores, verify evidence, and assemble compositions.
Routes across KB, cores, and boards
KB explains the criteria, /cores shows records and risks, and /boards constrains claims to specific hardware. These routes stay separate so learning, catalog browsing, and hardware evidence do not blur together.
KB article
How to evaluate an open FPGA core
How to evaluate an open FPGA core guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
License risks
License risks guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
Maturity levels
Maturity levels guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
Verification basics
Verification basics guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
FuseSoC and .core manifests
FuseSoC and .core manifests guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
How to read OpenCores records
How to read OpenCores records guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
Wishbone
Wishbone guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
AXI family
AXI family guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
Clock, reset, and CDC
Clock, reset, and CDC guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
How to integrate a core
How to integrate a core guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
How to read a resource report
How to read a resource report guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
How to run Verilator
How to run Verilator guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
How to run Yosys
How to run Yosys guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
How to port a core to a board
How to port a core to a board guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
How to write a core manifest
How to write a core manifest guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
Core composition
Core composition guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
Security and crypto cores
Security and crypto cores guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
Retro cores and legal risks
Retro cores and legal risks guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
RISC-V soft cores
RISC-V soft cores guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
Audio cores
Audio cores guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
Memory controllers
Memory controllers guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
KB article
Bus bridges and adapters
Bus bridges and adapters guidance for /cores users: evidence, risk, integration, and review decisions.
Catalog readers, maintainers, and reviewers.RAG-ready
Primary KB sources
OpenCoresUse OpenCores as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.OpenCores LicensingUse OpenCores Licensing as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.OpenCores WishboneUse OpenCores Wishbone as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.FuseSoC Package DirectoryUse FuseSoC Package Directory as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.FuseSoC CAPI2Use FuseSoC CAPI2 as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.FOSSi / LibreCoresUse FOSSi / LibreCores as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.CHIPS Alliance projectsUse CHIPS Alliance projects as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.CHIPS Alliance public scopeUse CHIPS Alliance public scope as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.OpenHW CORE-V verificationUse OpenHW CORE-V verification as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.CORE-V Verification StrategyUse CORE-V Verification Strategy as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.LiteXUse LiteX as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.AccelFury af-pdm-rxUse AccelFury af-pdm-rx as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.AccelFury GitHub organizationUse AccelFury GitHub organization as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.AccelFury core-templateUse AccelFury core-template as primary evidence, while keeping source claims, licensing, maturity, packaging, and integration signals separate during /cores review.