High-quality IP block library with docs and verification culture.

Small open RISC-V CPU used by OpenTitan.

Central open SoC builder and integration framework.

Шаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.

Bus protocol reference for OpenCores-era reusable IP.

Useful Wishbone-accessible debug core by ZipCPU author.

Canonical UART reference and common FuseSoC adaptations.

Industrial-grade open RISC-V core family source.

Example of DSP cores with Wishbone and claimed FPGA evidence.

Namespace index for public AccelFury repositories; useful as one source among many, not as a catalog priority lane.

Large curated arcade FPGA core ecosystem.

Raw PDM RX core на Verilog-2001 для MEMS microphones: генерирует PDM clock, сэмплирует 1-битный поток и выдаёт valid/ready stream. Не выполняет PDM-to-PCM decimation.

Tiny RISC-V core and FuseSoC-friendly ecosystem.

Specific CORE-V core with verification evidence.

Verification evidence model for CORE-V cores.

FuseSoC-listed open logic package family.

CPU, Wishbone and formal-heavy ecosystem.

Wishbone/AXI bridge and formal property library.

Open DRAM controller ecosystem used with LiteX.

Configurable RISC-V softcore used in LiteX ecosystem.

Verification helper for Wishbone cores.

High-value storage/networked design reference.

Basis for parsing .core fields.

Machine-readable core packages and integration metadata.

Security IP block with documentation and test culture.

Common SPI/SPI flash block in LiteX designs.

Formal verification flow signal.

Modern Python-based HDL ecosystem source.

Modern Ethernet core comparison point.

Well-documented VHDL RISC-V SoC candidate.

Compact softcore with strong FPGA relevance.

AXI components and infrastructure.

Reusable cells widely used by PULP projects.

Linux-capable RISC-V core lineage.

Common Wishbone interconnect package.

Generic FIFO baseline.

Modern adaptation of OpenCores UART16550.

Common GitHub UART implementation.

CDC helpers for composition planner.

Open cache candidate.

Ethernet candidate with OpenCores ethmac relation.

FM sound core useful for retro/audio category.

Debug infrastructure for composition planner.

Useful storage peripheral for SoC designs.

Stream FIFO/width conversion baseline.

Open RISC-V core family for comparison.

Minimal SoC building block.

Useful crypto/security reference.

GPIO reference with register docs.

High-quality UART documentation example.

Good KB reference for graphics pipelines.

I2C reference with docs.

Primitive library reference.

SPI device reference.

Historical open soft CPU baseline.

Open PCIe ecosystem core.

Discovery source for reference designs and board demos.

LiteX complex link core.

Open flow support signal.

CHIPS Alliance root-of-trust IP.

Crypto hash block with docs.

Important Chisel generator ecosystem.

AXI component library and comparison source.

Ethernet MAC/UDP/IP stack candidate.

Open P&R support signal.

Open synthesis toolchain for support matrix.

Tang/Gowin board examples after review.

Useful historical learning examples.

Useful KB examples but must be marked educational/demo.

Beginner examples for KB, not production cores.

Amaranth ecosystem discovery root.

Reusable SystemVerilog library.

Floating-point arithmetic core family.

Manycore RISC-V candidate.

High-end RISC-V research core.

VGA timing core candidate.