News
YADRO synthesis school 2026/27: apply by 31 October
October 8, 2026· YADRO FPGA event coverage· Note
In-person selection ends on 10 October; applications are accepted until 31 October. Free study at university clusters and online.
Verilog / SystemVerilogFPGA + SoCEducation
Dates and format
YADRO announced its Digital Circuit Synthesis School for autumn 2026–spring 2027. In-person cluster selection ends on 10 October; the application form is available until 31 October 2026. Participation is free. Sessions are scheduled for Saturdays, 12:00–15:00 Moscow time.
Before applying
In-person participants must be students of the corresponding university and pass selection. Online participants provide their own equipment. The website currently shows the previous season’s curriculum, which may change. Exact first and last session dates have not been specified.