C, SystemVerilog, formal verification and co-simulation. Intake is closed; notifications about future openings are available.
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YADRO’s education catalogue lists a three-day hackathon in Moscow in 2027. Exact dates and participation requirements remain unannounced.
In-person selection ends on 10 October; applications are accepted until 31 October. Free study at university clusters and online.
Recordings from thirteen FPGA-Systems events, an FPGA/ASIC meeting in Minsk, five SoC Design Challenge editions and an FPGA workshop.
14 November at Lobachevsky University and online: RISC-V modelling, SoC benchmarking on FPGA, FFT architectures, JTAG, Verihogg and FPGA optimisation.
FPGA.camp opened its first version as a compact engineering hub: news, journal, projects, classifieds, meetups, boards, KB, and Chat.
Yosys is a baseline open-source framework for Verilog RTL synthesis and formal-related flows.
Verilator compiles Verilog/SystemVerilog into C++/SystemC and is used in regression flows.
The classifieds section includes source-linked FPGA job cards: NTC Raduga, MTUCI, and Informtest.
The /chat section accepts FPGA questions and sends them through a server-side OpenRouter endpoint.