C, SystemVerilog, formal verification and co-simulation. Intake is closed; notifications about future openings are available.
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YADRO’s education catalogue lists a three-day hackathon in Moscow in 2027. Exact dates and participation requirements remain unannounced.
In-person selection ends on 10 October; applications are accepted until 31 October. Free study at university clusters and online.
Recordings from thirteen FPGA-Systems events, an FPGA/ASIC meeting in Minsk, five SoC Design Challenge editions and an FPGA workshop.
FPGA.camp opened its first version as a compact engineering hub: news, journal, projects, classifieds, meetups, boards, KB, and Chat.
Starter Tang board on Gowin GW1NR-9: 8640 LUT4, HDMI, TF slot, USB-JTAG, and USB-UART.
GW2AR-18 board: 20736 LUT4, SDR SDRAM, HDMI, TF slot, and BL616 debugger.
The /chat section accepts FPGA questions and sends them through a server-side OpenRouter endpoint.
The April 30, 2026 webinar compares when high-level code is enough and when dedicated hardware logic in Verilog is the right tool.
AMD’s new engineering article covers system-level verification for Versal designs that combine PL, AI Engines, NoC, and software.