News
YADRO SoC verification course: programme and intake status
October 8, 2026· YADRO FPGA event coverage· Note
C, SystemVerilog, formal verification and co-simulation. Intake is closed; notifications about future openings are available.
Verilog / SystemVerilogFPGA + SoCEducation
Programme
SoC verification is part of YADRO’s 2026/27 practical courses. Topics include C tests, SystemVerilog testbenches, formal verification and RTL co-simulation.
Participation
Intake is closed. The format is online or at the Moscow office. Exact dates for this track are unannounced; notification signup is available. Status checked on 8 October 2026.