maintainedApril 26, 2026BSD-2-Clause

LiteX

Python-based FPGA SoC builder for cores, buses, soft CPUs, and board targets.

PythonMigenRISC-VSoC

LiteX is useful for learning and research SoC projects on FPGA targets.

The card links to the official enjoy-digital/litex repository.

More projects

MaintainedApril 26, 2026ISC

Open SYnthesis Suite for Verilog RTL synthesis and formal-related flows.

VerilogRTLILSynthesisFormal

MaintainedApril 26, 2026ISC

Portable FPGA place-and-route tool with support for several FPGA families.

C++PnRGowinECP5

MaintainedApril 26, 2026LGPL-3.0 / Artistic-2.0

Open-source SystemVerilog simulator and lint system.

SystemVerilogC++SystemCLint