High-quality IP block library with docs and verification culture.
Auto indexedApache-2.0
/cores
Core comparison
Comparison helps you see quickly which core carries less license, review, and integration risk.
Pick 2–4 cores
How to build a shortlistEnter comma-separated slugs or add the cards below. Compare only keeps unique slugs and a maximum of four records.Ibex
P0Small open RISC-V CPU used by OpenTitan.
Auto indexedApache-2.0
LiteX
P0Central open SoC builder and integration framework.
Auto indexedBSD-2-Clause-like until checked
Шаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.
Manually reviewedCERN-OHL-S-2.0 + AGPL + CC-BY-SA
Bus protocol reference for OpenCores-era reusable IP.
Auto indexedpublic-domain-like per OpenCores WISHBONE page
Useful Wishbone-accessible debug core by ZipCPU author.
Auto indexedGPL
Canonical UART reference and common FuseSoC adaptations.
Auto indexedunknown until checked
Industrial-grade open RISC-V core family source.
Auto indexedSolderpad
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
OpenTitan IP blocks
security/root-of-trust/IP blocks
Manual review is required.
High-quality IP block library with docs and verification culture.
LicenseApache-2.0License riskApache-2.0: Current metadata does not show an explicit license blocker.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogApache-2.0unknown
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
Ibex
processor/RISC-V
Manual review is required.
Small open RISC-V CPU used by OpenTitan.
LicenseApache-2.0License riskApache-2.0: Current metadata does not show an explicit license blocker.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogApache-2.0unknown
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
LiteX
SoC builder/generator
Manual review is required.
Central open SoC builder and integration framework.
LicenseBSD-2-Clause-like until checkedLicense riskBSD-2-Clause-like until checked: Current metadata does not show an explicit license blocker.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
Migen/Python/VerilogBSD-2-Clause-like until checkedMemory
PriorityP2 review: entry kept for review depth, edge cases, or future ingestion.Review statusReview status: Manually reviewed. A manual pass exists, but evidence still needs link-level checking.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
AccelFury core-template
generator / template / IP methodology
This is a template/example, not a standalone core.
Generated projects require separate review.
Шаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.
LicenseCERN-OHL-S-2.0 + AGPL + CC-BY-SALicense riskCERN-OHL-S-2.0 + AGPL + CC-BY-SA: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q42
Use36
Int70
Ver18
Rust/SystemVerilog/TypeScriptCERN-OHL-S-2.0 + AGPL + CC-BY-SAunknown
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores Wishbone
bus/Wishbone
Manual review is required.
Bus protocol reference for OpenCores-era reusable IP.
Licensepublic-domain-like per OpenCores WISHBONE pageLicense riskpublic-domain-like per OpenCores WISHBONE page: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use54
Int52
Ver18
Specificationpublic-domain-like per OpenCores WISHBONE pageunknownWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores WBScope
verification/logic analyzer
Manual review is required.
Useful Wishbone-accessible debug core by ZipCPU author.
LicenseGPLLicense riskGPL: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
VerilogGPLJTAG/debugWishbone
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: opencores. This is record provenance, not endorsement or quality proof.
OpenCores UART16550
peripheral/UART
The license requires manual review.
The source appears stale or legacy.
Canonical UART reference and common FuseSoC adaptations.
Licenseunknown until checkedLicense riskunknown until checked: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q48
Use72
Int76
Ver22
Verilogunknown until checkedUART
PriorityP0 launch: this record is important for baseline catalog coverage and fast comparisons.Review statusReview status: Auto indexed. Manual review is still required beyond seed/index metadata.Source typeSource type: github. This is record provenance, not endorsement or quality proof.
OpenHW CORE-V cores
processor/RISC-V
Manual review is required.
Industrial-grade open RISC-V core family source.
LicenseSolderpadLicense riskSolderpad: HDL/docs/tests/examples still need manual review.
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogSolderpadunknown