Efinix Sapphire RV64 SoC

Configurable soft RISC-V SoC from Efinix: 1 to 4 64-bit cores, optional SV39 MMU, L1 and L2 caches, DDR3, LPDDR4x and HyperRAM controller for Efinix FPGAs; licence not stated.

CPUs and computeNo license foundM1 · Prototype

Worth knowing

Info

Requires independent simulation, synthesis, timing, board and license review before production use.

Facts

The source is not on GitHub — an editor checks tests and license manually.

Maturity
M1 · Prototype
License
No license found
Tests
not found
CI
not found
Formal verification
not found
FuseSoC
not found

Source exists, but no tests were found. How maturity is assigned

Purpose

Configurable 64-bit RISC-V core for Efinix Trion, Titanium and Topaz FPGAs.

AXI3AXI4APB3GPIOSPII2CUARTAXI3AXI4APB3Efinity IDEEfinity IP ManagerEfinity RISC-V Embedded Software IDE

Boards

No one has confirmed a board run yet.

Add evidence

Sources

How to check it locally
  • Try a synthesis smoke run with: Efinity IDE, Efinity IP Manager, Efinity RISC-V Embedded Software IDE.
Scores and how they are computed

License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.

Quality26
Verification15
License15
Docs35
Integration55
Usefulness0
Beginner0
Professional21
Confidence40

Similar cores

VexiiRiscv

Checked on GitHub

MIT-licensed RISC-V CPU from SpinalHDL, successor of VexRiscv: RV32/64, optional SV32/SV39 MMU, Linux capable, written in SpinalHDL, generates Verilog.

CPUs and computeSpinalHDL (Scala)MITM2 · Simulation-testedupdated 4 days ago